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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion mcp data sheet tm
ds05-50405-1e fujitsu semiconductor data sheet 3 stacked mcp (multi-chip package) flash & flash & fcram cmos 128m ( 16) burst flash memory & 128m ( 16) burst flash memory & 128m ( 16) page/burst mobile fcram tm mb84sf6h6h6l2 -70 n n n n features ? power supply voltage flash _1 & 2: v cc f = 1.65 v to 1.95 v fcarm: v cc r = 2.5 v to 3.1 v, v ccq r = 1.65 v to 1.95 v ? high performance 11 ns maximum burst read access time, 56 ns maximum random access time (flash_1 & flash_2) 11 ns maximum burst read access time, 70 ns maximum random access time (fcram tm ) (continued) n n n n product lineup *: all of v cc f_1, v cc f_2 and v cc r must be the same level when either part is being accessed. n n n n pac k ag e flash_1 & flash_2 fcram supply voltage (v) v cc f_1 & 2* = 1.8 v v cc r* = 3.0 v i/o supply voltage (v) v ccq r = 1.65 v to 1.95 v v ccq r = 1.65 v to 1.95 v synchronous/ burst max latency time (ns) 71 max burst access time (ns) 11 11 max oe access time (ns) 11 asynchronous max address access time (ns) 56 70 max ce access time (ns) 56 70 max oe access time (ns) 11 40 max page access time (ns) 20 115-ball plastic fbga bga-115p-m03 +0.15v C0.15v +0.10v C0.50v
mb84sf6h6h6l2 -70 2 ? operating temperature C30 c to +85 c ? package 115-ball bga flash memory_1 & flash memory_2 ?0.13 m process technology ? single 1.8 volt read, program and erase (1.65 v to 1.95 v) ? simultaneous read/write operation (dual bank) ? flexbank tm * 1 bank a: 16mbit (4 kwords 8 and 32 kwords 31) bank b: 48mbit (32 kwords 96) bank c: 48mbit (32 kwords 96) bank d: 16mbit (4 kwords 8 and 32 kwords 31) ? high performance burst frequency reach at 66mhz burst access times of 11 ns @ 30 pf at industrial temperature range asynchronous random access times of 56 ns (at 30 pf) ? programmable burst interface linear burst: 8, 16, and 32 words with wrap-around ? minimum 100,000 program/erase cycles ? sector erase architecture eight 4 kwords, two hundred fifty-four 32 kwords sectors, eight 4 kwords sectors. any combination of sectors can be concurrently erased. also supports full chip erase. ?wp input pin (wp _1, wp _2) at v il , allows protection of "outermost" 4 4 k words on low, high end or both ends of boot sectors, regardless of sector protection/unprotection status. ? accelerate pin (acc) at v acc , increases program performance. ; all sectors locked when acc = v il ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready output (ry/by ) in synchronous mode, indicates the status of the burst read. in asynchronous mode, indicates the status of the internal program and erase function. ? automatic sleep mode when address remain stable, the device automatically switches itself to low power mode ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? hardware reset pin (reset ) hardware method to reset the device for reading array data ? please refer to mbm29bs12dh datasheet in deteiled function (continued)
mb84sf6h6h6l2 -70 3 (continued) fcram tm * 3 ? power dissipation operating : 35 ma max standby : 300 m a max (no clk) ? various partial power down mode sleep : 10 m a max 16m partial : 120 m a max 32m partial : 150 m a max ? power down control by ce2r ? 8 words page read access capability ? burst read/write access capability ? byte write control: lb (dq 7 to dq 0 ), ub (dq 15 to dq 8 ) *1: flexbank tm is a trademark of fujitsu limited, japan. *2: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. *3: fcram tm is a trademark of fujitsu limited, japan.
mb84sf6h6h6l2 -70 4 n n n n pin assignment (top view) marking side (bga-115p-m03) d1 n.c. d8 a 13 d7 a 9 d6 a 20 d5 ry/by d4 a 18 d3 a 5 d2 d9 a 21 f8 n.c. f7 dq 6 f4 dq 1 f3 v ss f2 f9 a 16 g8 dq 15 g7 dq 13 g6 dq 4 g5 dq 3 g4 dq 9 g3 oe g2 g9 n.c. e8 a 14 e7 a 10 e4 a 17 e3 a 4 e2 e9 a 22 h8 dq 7 h7 dq 12 h6 v ccq r h5 v cc f_1 h4 dq 10 h3 dq 0 h2 h9 v ss j8 dq 14 j7 dq 5 j6 n.c. j5 dq 11 j4 dq 2 j3 dq 8 c8 a 12 c7 a 19 c6 ce2r c5 reset c4 ub c3 a 6 a 7 c2 c9 a 15 a 11 a 8 we acc lb f6 n.c. f5 v cc r e6 wp_2 e5 n.c. n.c. n.c. n.c. n.c. b10 b9 a10 a9 n.c. n.c. n.c. n.c. cef_2 clk j9 n.c. n.c. d10 n.c. f10 n.c. g10 n.c. e10 n.c. h10 n.c. c10 n.c. n.c. n.c. n.c. n.c. n.c. n.c. v cc f_2 v ss n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. j10 e1 f1 g1 h1 j1 j2 k10 k9 k8 l9 k1 n.c.. n.c. b1 b2 a2 a1 n.c. l10 n.c. n.c. n.c. n10 n9 p9 n.c. p10 l1 k2 k3 k4 k5 k6 k7 n.c. n.c. n1 n2 l2 n.c. p1 p2 l3 l4 l5 l6 l7 l8 a 2 a 0 cef_1 a 1 ce1r a 3 wp_1 n.c. adv n.c. n.c. n.c. n.c. n.c. n.c. m1 m2 m3 m4 m5 m6 m7 m8 m9 m10
mb84sf6h6h6l2 -70 5 n n n n pin description pin name input/ output description a 22 to a 0 i address inputs (common) dq 15 to dq 0 i/o data inputs/outputs (common) ce f_1 i chip enable (flash_1) ce f_2 i chip enable (flash_2) ce 1r i chip enable (fcram) ce2r i chip enable (fcram) oe i output enable (common) we i write enable (common) ry/by o ready output. (in asynchronous mode, ry/by output) / (low active) (flash_1 & flash_2) & wait signal output (fcram) ub i upper byte control (fcram) lb i lower byte control (fcram) adv i address data valid (common) clk i clk input (common) reset i hardware reset pin/sector protection unlock (flash_1& flash_2) wp _1 i write protect (flash_1) wp _2 i write protect (flash_2) acc i program acceleration (flash_1&2) n.c. no internal connection v ss power device ground (common) v cc f_1 power device power supply (flash_1) v cc f_2 power device power supply (flash_2) v cc r power device power supply (fcram) v ccq r power i/o power supply (fcram)
mb84sf6h6h6l2 -70 6 n n n n block diagram wait v cc f_1 v ss cef_1 reset ry/by wp_1 oe we clk adv acc 128 mbit burst flash memory cef_1 reset wp oe we clk adv ry/by v cc f_2 v ss v cc r v ccq r v ss cef_2 128 mbit burst flash memory 128 mbit burst fcram cef_2 reset wp oe we clk adv ce1r ce2r ub lb ub lb oe we clk adv ry/by wait ce1r ce2r wp_2 a 22 to a 0 a 22 to a 0 a 22 to a 0 a 22 to a 0 dq 15 to dq 0 dq 15 to dq 0 dq 15 to dq 0 dq 15 to dq 0
mb84sf6h6h6l2 -70 7 n n n n device bus operations ? asynchronous operation (continued) operation ce f_1 ce f_2 ce 1r ce2r oe we lb ub a 22 to a 0 dq 7 to dq 0 dq 15 to dq 8 adv reset wp _1 wp _2 acc ry /by(wait ) full standby hh h h xxxx x high-z high-z xhxxx high -z output disable* 1 hh l h hhxx x* 3 high-z high-z x hxxx high -z hl hh hhxxx x lhhh hhxxx x flash_1 or 2 asynchronous read - addresses latched* 2 lh hh lhxx addr in d out d out lhxxx high -z hl flash_1or 2 write - we address latched* 4 lh hhhlxx addr in d in d in lh x* 5 x* 5 h* 5 high -z hl flash_1or 2 write - adv address latched* 4 lh hhh xx addr in d in d in h x* 5 x* 5 h* 5 high -z hl fcram no read hh l h lhhh valid high-z high-z *6 x x x x high -z fcram read (upper byte) hh l h lhhl valid high-z output valid *6 x x x x high -z fcram read (lower byte) hh l h lhlh valid output valid high-z *6 x x x x high -z fcram read (word) hh l h lhll valid output valid output valid *6 x x x x high -z fcram page read hh l h lhl/hl/h valid *7 *7 *6 x x x x high -z fcram no write hh l h* 9 h* 9 lhh valid invalid invalid *6 x x x x high -z fcram write (upper byte) hh l h* 9 h* 9 lh l valid invalid input valid *6 x x x x high -z fcram write (lower byte) hh l h* 9 h* 9 llh valid input valid invalid *6 x x x x high -z fcram write (word) hh l h* 9 h* 9 ll l valid input valid input valid *6 x x x x high -z flash_1 boot sector write protection* 5 xxxxxxxxx x x x hl * 5 xx high -z flash_2 boot sector write protection* 5 xxxxxxxxx x x x hxl * 5 x high -z flash_1 &2 all sector write protection* 5 xx h h xxxx x x x x h xxl * 5 high -z flash_1 & flash_2 reset xx h h xxxx x high-z high-z xlxxx high -z fcram power down* 8 xx x l xxxx x high-z high-z xxxxx high -z
mb84sf6h6h6l2 -70 8 (continued) legend : l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. see dc characteristics in n electrical characteristics for voltage levels. *1 : fcram output disable mode(ce 1r = l)should not be kept this logic condition longer than 4 ms. please contact local fujitsu representative for the relaxation of 4 ms limitation. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : can be either v il or v ih but must be valid before read or write. *4 : write operation: at asynchronous mode, addresses are latched on the last falling edge of we pulse while adv is held low or rising edge of adv pulse whichever comes first. data is latched on the 1st rising edge of we . *5 : at wp =v il , sa0 to sa3 and sa266 to sa269 are protected. at acc=v il , all sectors are protected. *6 : "l" for address pass through and "h" for address latch on the rising edge of adv. *7 : output is either valid or high-z depending on the level of ub and lb input. *8 : power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to 2. functional description power down in n 128m fcram characteristics for mcp for the details. *9 : oe can be v il during write operation if the following conditions are satisfied; (1) write pulse is initiated by ce 1r (refer to ce 1r controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe stays v il during write cycle.
mb84sf6h6h6l2 -70 9 ? synchronous operation (continued) operation ce f_1 ce f_2 ce 1r ce2r oe we lb ub a 22 to a 0 dq 7 to dq 0 dq 15 to dq 8 clk* 1 adv reset wp _1 wp _2 acc ry /by(wait ) flash_1 or 2 load starting burst address (clk latch)* 3 lh hhxhxx addr in xx *9 hxxx high -z hl flash_1 or 2 advance burst to next address with appropriate data presented on the data bus* 3 lh hhlhxxx d out d out *9 hhxxx high -z hl flash_1 or 2 te r m i n a t e current burst read cycle hh h hxhxx x x high- z *9 xhxxx high -z flash_1 or 2 te r m i n a t e current burst read cycle and start new burst read cycle lh hhxhxx addr in d out d out *9 hxxx high -z hl flash_1 or 2 burst suspend lh hhhhxxx high-z high-z xhhxxx high -z hl flash_1 or 2 synchronous write - we address latched* 12 lh hhhlxx addr in d in d in h/l l h x* 4 x* 4 h* 4 high -z hl flash_1 or 2 synchronous write - clk address latched* 12 lh hhh xx addr in din din *9 lh x* 4 x* 4 h* 4 high -z hl flash_1 or 2 synchronous write -adv address latched * 12 lh hhh xx addr in d in d in h/l h x* 4 x* 4 h* 4 high -z ll flash_1& 2 te r m i n a t e current burst read via reset xx h hxhxxx high- z high- z xxlxxx high -z fcram start address* 2 latch hh l h x* 5 x* 5 x* 6 x* 6 valid * 7 high- z* 8 high- z* 8 *9 xxxx high -z* 14 fcram advance burst read to next address* 2 hh l hlh x* 6 x* 6 x output valid * 10 output valid * 10 *9 hxxxx out- put valid fcram burst read suspend* 2 hh l hhh x* 6 x* 6 x high-z high-z *9 hxxxx high -z* 15
mb84sf6h6h6l2 -70 10 (continued) legend : l = v il , h = v ih , x can be either v il or v ih , = positive edge, = positive edge of low pulse, high-z = high impedance. see dc characteristics in n electrical characteristics for voltage levels. *1 : default state is x after power-up. *2 : fcram output disable mode(ce 1r = l)should not be kept this logic condition longer than 4 ms. please contact local fujitsu representative for the relaxation of 4 ms limitation. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : at wp =v il , sa0 to sa3 and sa266 to sa269 are protected. at acc=v il , all sectors are protected. *5 : can be either v il or v ih except for the case the both of oe and we are v il . it is prohibited to bring the both of oe and we to v il . *6 : can be either v il or v ih but must be valid before read or write is determined. and once ub and lb inputs are determined, it must not be changed until the end of burst. *7 : once valid address is determined, input address must not be changed during adv =l. in case a 22 , h must not be changed until end of burst. *8 : if oe =l, output is either invalid or high-z depending on the level of ub and lb input. if we =l, input is invalid. if oe =we =h, output is high-z. *9 : valid clock edge shall be set on either positive or negative edge through cr (configration register) set. *10 : output is either valid or high-z depending on the level of ub and lb input. *11 : input is either valid or invalid depending on the level of ub and lb input. *12 : write operation: at synchronous mode, addresses are latched on the falling edge of we while adv is held low, active edge of clk while adv is held low or rising edge of adv whichever happens first. data is latched on the 1st rising edge of we . *13 : when device is operationg in "we single clock pulse control" mode, we is don't care once write operation is determined by we low pulse at the begginig of write access together with address latcing. write suspend feature is not supported in "we single clock pulse control" mode. *14 : output is either high-z or invalid depending on the level of oe and we input. *15 : keep the level from previous cycle except for suspending on last data. refere to 2. functional description wait output function in n 128m fcram characteristics for mcp for the details. *16 : wait output is driven in high level during write operation. operation ce f_1 ce f_2 ce1 r ce2r oe we lb ub a 22 to a 0 dq 7 to dq 0 dq 15 to dq 8 clk* 1 adv reset wp _1 wp _2 acc ry /by(wait ) fcram advance burst write to next address* 2 hh l hh l* 13 x* 6 x* 6 x input valid * 11 input valid * 11 *9 hxxxx high -z* 16 fcram burst write suspend* 2 hh l hh h* 13 x* 6 x* 6 x input invalid input invali d *9 hxxxx high -z* 15 fcram te r m i n a t e burst read hh hlh x* 6 x* 6 x high- z high- z xhx xxx high -z fcram te r m i n a t e burst write hh hhl x* 6 x* 6 x high- z high- z xhx xxx high -z
mb84sf6h6h6l2 -70 11 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is C0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to C1.0 v for periods of up to 10 ns. maximum dc voltage on input or i/o pins is v cc f_1 + 0.3 v or v cc f_2 +0.3v or v ccq r + 0.2 v . during voltage transitions, input or i/o pins may overshoot to v cc f + 1.0 v or v cc f_2 + 1.0 v or v ccq r + 1.0 v for periods of up to 5 ns. *3 : minimum dc input voltage on acc pin is C0.5 v. during voltage transitions, acc pin may undershoot v ss to C2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed +9.0 v. maximum dc input voltage on acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions note : operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating conditionranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg C55 +125 c ambient temperature with power applied t a C30 +85 c voltage with respect to ground all pins except reset , acc * 1 * 2 v in , v out C0.3 v cc f_1 +0.3 v v cc f_2 +0.3 v v ccq r +0.3 v v cc r supply * 1 v cc rC0.3+3.6v v cc f_1/ v cc f_2 / v ccq r supply * 1 v cc f_1, v cc f_2, v ccq r C0.3 +2.5 v acc * 1, * 3 v acc C0.5 +10.5 v parameter symbol value unit min max ambient temperature t a C30 +85 c v cc r supply voltages v cc r +2.5 +3.1 v v cc f/v ccq r supply voltages v cc f_1, v cc f_2, v ccq r+1.65 +1.95 v
mb84sf6h6h6l2 -70 12 n n n n electrical characteristics ? dc characteristics (continued) parameter sym- bol conditions value unit min typ max input leakage current i li v in = v ss to v cc f, v ccq r C1.0 +1.0 a output leakage current i lo v out = v ss to v cc f, v ccq r C1.0 +1.0 a flash v cc f current (standby) (flash_1 & flash_2) i sb1 f ce f = reset = v cc f 0.2 v * 9 1* 7 50* 7 a flash_1 & 2 v cc f current (standby, reset) (flash_1 & flash_2) i sb2 f reset = v ss 0.2 v, clk = v il * 9 1* 7 50* 7 a flash_1 & 2 v cc f current (automatic sleep mode)* 3 (flash_1 & flash_2) i sb3 f v cc f = v cc f max, ce f = v ss 0.2 v, reset = v cc f 0.2 v, v in = v cc f 0.2 v or v ss 0.2 v * 9 1* 7 50* 7 a flash v cc f active burst read current (flash_1 or flash_2) i cc1 f ce f = v il , oe = v ih , we = v ih , 66 mhz * 9 15 30 ma flash v cc f active asynchronous read current* 1 (flash_1 or flash_2) i cc2 f ce f = v il , oe = v ih , we = v ih * 9 10 mhz 20 30 ma 5 mhz 10 15 flash v cc f active current * 2 (flash_1 or flash_2) i cc3 f ce f = v il , oe = v ih , v pp = v ih * 9 15 40 ma flash v cc f active current (read-while-program ) * 4 (flash_1 or flash_2) i cc4 f ce f = v il , oe = v ih * 9 25 60 ma flash v cc f active current (read-while-erase) * 4 (flash_1 or flash_2) i cc5 f ce f = v il , oe = v ih * 9 25 60 ma fcram v cc r power down current* 5 i ddps rv cc r = v cc r max, v ccq r = v ccq r max, v in = v ih or v il , ce2r 0.2 v sleep 10 a i ddp8 r 16m partial 120 a i ddp16 r 32m partial 150 a fcram v cc r standby current* 5, * 8 i sbs r v cc r = v cc r max, v ccq r = v ccq r max, v in (including clk) = v ih or v il , ce 1r = ce2r = v ih 1.5ma i sb1 r v cc r = v cc r max, v ccq r = v ccq r max, v in (including clk) 0.2 v or v in (including clk) 3 v ccq r C 0.2 v, ce 1r = ce2r 3 v ccq r C 0.2 v 300 a i sb2 r v ccq r = v ccq r max, t ck = min, v in 0.2 v or v in 3 v ccq r C 0.2 v, ce 1r = ce2r 3 v ccq r C 0.2 v 350 a
mb84sf6h6h6l2 -70 13 (continued) *1 : the i cc current listed includes both the dc operating current and the frequency dependent component. *2 : i cc active while embedded algorithm (program or erase) is in progress. *3 : automatic sleep mode enables the low power mode when address remains stable for t acc + 60 ns. *4 : embedded alogorithm (program or erase) is in progress. (@5 mhz) *5 : fcram dc current is measured after following power-up timing. *6 : v cc means v cc f_1 or v cc f_2 or v ccq r. *7 : actual standby current is twice of what is indicated in the table, due to two flash chips embedment withn one device. *8 : i out depemds on the output load comditions. *9 : ce f means ce f_1 or ce f_2. *10 : applicable for only v cc f_1 or v cc f_2. parameter symbol conditions value unit min typ max fcram v cc r active current * 5, * 8 i cc1 r v cc r = v cc r max, v ccq r = v ccq r max, v in = v ih or v il , ce 1r = v il and ce2r = v ih , i out = 0 ma t rc / t wc = min 35 ma i cc2 rt rc / t wc = 1 s 5 ma fcram v cc r page read current * 5, * 8 i cc3 r v cc r = v cc r max, v ccq r = v ccq r max, v in = v ih or v il , ce 1r = v il and ce2r = v ih , i out = 0 ma, t prc = min 15ma fcram v cc r burst access current * 5, * 8 i cc4 r v cc r = v cc r max, v ccq r = v ccq r max, v in = v ih or v il , ce 1r = v il and ce2r = v ih , t ck = t ck min, bl = continuous, i out = 0 ma 30ma input low level v il C0.3 v cc 0.2 * 6 v input high level v ih v cc C 0.4 * 6 v cc + 0.2 * 6 v output low voltage level v ol fi ol = 0.1 ma flash_1 or flash_2 0.1v v ol ri ol = 1.0 ma fcram 0.4 v output high voltage level v oh fi oh = C 0.1 ma flash_1 or flash_2 v cc f C 0.1 v v oh r v ccq r = v ccq r min, i oh = C 0.5 ma fcram 1.4 v voltage for acc program acceleration* 10 v acc 8.59.5v
mb84sf6h6h6l2 -70 14 ? ac characteristics ?ce timing ? timing diagram for alternating ram to flash ? nor flash_1&2 characteristics please refer to n 128m burst flash memory caracteristics for mcp. ? fcram characteristics please refer to n 128m fcram characteristics for mcp. parameter symbol condition value unit jedec standard min max ce recover time t ccr 0ns ce f hold time t chold 3ns ce 1r high to we invalid time for standby entry t chwx 10ns ce f_1 or t ccr t ccr ce 1r ce2r t ccr t ccr we t chwx t chold ce f_2
mb84sf6h6h6l2 -70 15 n n n n 128m burst flash memory characteristics for mcp 1. flexible sector-erase architecture on flash memory ? sixteen 4k words, and one hundred twenty-six 32k words. ? individual-sector, multiple-sector, or bulk-erase capability. sector architecture sa0 : 8kb sa1 : 8kb sa2 : 8kb sa3 : 8kb sa4 : 8kb sa5 : 8kb sa6 : 8kb sa7 : 8kb sa8 : 64kb sa9 : 64kb sa10 : 64kb sa11 : 64kb sa12 : 64kb sa13 : 64kb sa14 : 64kb sa15 : 64kb sa16 : 64kb sa17 : 64kb sa18 : 64kb sa19 : 64kb sa20 : 64kb sa21 : 64kb sa22 : 64kb sa23 : 64kb sa24 : 64kb sa25 : 64kb sa26 : 64kb sa27 : 64kb sa28 : 64kb sa29 : 64kb sa30 : 64kb sa31 : 64kb sa32 : 64kb sa33 : 64kb sa34 : 64kb sa35 : 64kb sa36 : 64kb sa37 : 64kb sa38 : 64kb sa39 : 64kb sa40 : 64kb sa41 : 64kb sa42 : 64kb sa43 : 64kb sa44 : 64kb sa45 : 64kb sa46 : 64kb sa47 : 64kb sa48 : 64kb sa49 : 64kb sa50 : 64kb sa51 : 64kb sa52 : 64kb sa53 : 64kb sa54 : 64kb sa55 : 64kb sa56 : 64kb sa57 : 64kb sa58 : 64kb sa59 : 64kb sa60 : 64kb sa61 : 64kb sa62 : 64kb sa63 : 64kb sa64 : 64kb sa65 : 64kb sa66 : 64kb sa67 : 64kb sa68 : 64kb sa69 : 64kb sa70 : 64kb sa199: 64kb sa200: 64kb sa201: 64kb sa202: 64kb sa203: 64kb sa204: 64kb sa205: 64kb sa206: 64kb sa207: 64kb sa208: 64kb sa209: 64kb sa210: 64kb sa211: 64kb sa212: 64kb sa213: 64kb sa214: 64kb sa215: 64kb sa216: 64kb sa217: 64kb sa218: 64kb sa219: 64kb sa220: 64kb sa221: 64kb sa222: 64kb sa223: 64kb sa224: 64kb sa225: 64kb sa226: 64kb sa227: 64kb sa228: 64kb sa229: 64kb sa230: 64kb sa231: 64kb sa232: 64kb sa233: 64kb sa234: 64kb sa235: 64kb sa236: 64kb sa237: 64kb sa238: 64kb sa239: 64kb sa240: 64kb sa241: 64kb sa242: 64kb sa243: 64kb sa244: 64kb sa245: 64kb sa246: 64kb sa247: 64kb sa248: 64kb sa249: 64kb sa250: 64kb sa251: 64kb sa252: 64kb sa253: 64kb sa254: 64kb sa255: 64kb sa256: 64kb sa257: 64kb sa258: 64kb sa259: 64kb sa260: 64kb sa261: 64kb sa262: 8kb sa263: 8kb sa264: 8kb sa265: 8kb sa266: 8kb sa267: 8kb sa268: 8kb sa269: 8kb sa71 : 64kb sa72 : 64kb sa73 : 64kb sa74 : 64kb sa75 : 64kb sa76 : 64kb sa77 : 64kb sa78 : 64kb sa79 : 64kb sa80 : 64kb sa81 : 64kb sa82 : 64kb sa83 : 64kb sa84 : 64kb sa85 : 64kb sa86 : 64kb sa87 : 64kb sa88 : 64kb sa89 : 64kb sa90 : 64kb sa91 : 64kb sa92 : 64kb sa93 : 64kb sa94 : 64kb sa95 : 64kb sa96 : 64kb sa97 : 64kb sa98 : 64kb sa99 : 64kb sa100: 64kb sa101: 64kb sa102: 64kb sa103: 64kb sa104: 64kb sa105: 64kb sa106: 64kb sa107: 64kb sa108: 64kb sa109: 64kb sa110: 64kb sa111: 64kb sa112: 64kb sa113: 64kb sa114: 64kb sa115: 64kb sa116: 64kb sa117: 64kb sa118: 64kb sa119: 64kb sa120: 64kb sa121: 64kb sa122: 64kb sa123: 64kb sa124: 64kb sa125: 64kb sa126: 64kb sa127: 64kb sa128: 64kb sa129: 64kb sa130: 64kb sa131: 64kb sa132: 64kb sa133: 64kb sa134: 64kb sa135: 64kb sa136: 64kb sa137: 64kb sa138: 64kb sa139: 64kb sa140: 64kb sa141: 64kb sa142: 64kb sa143: 64kb sa144: 64kb sa145: 64kb sa146: 64kb sa147: 64kb sa148: 64kb sa149: 64kb sa150: 64kb sa151: 64kb sa152: 64kb sa153: 64kb sa154: 64kb sa155: 64kb sa156: 64kb sa157: 64kb sa158: 64kb sa159: 64kb sa160: 64kb sa161: 64kb sa162: 64kb sa163: 64kb sa164: 64kb sa165: 64kb sa166: 64kb sa167: 64kb sa168: 64kb sa169: 64kb sa170: 64kb sa171: 64kb sa172: 64kb sa173: 64kb sa174: 64kb sa175: 64kb sa176: 64kb sa177: 64kb sa178: 64kb sa179: 64kb sa170: 64kb sa181: 64kb sa182: 64kb sa183: 64kb sa184: 64kb sa185: 64kb sa186: 64kb sa187: 64kb sa188: 64kb sa191: 64kb sa192: 64kb sa193: 64kb sa194: 64kb sa195: 64kb sa196: 64kb sa197: 64kb sa198: 64kb sa189: 64kb sa190: 64kb 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0a0000h 0a8000h 0b0000h 0b8000h 0c0000h 0c8000h 0d0000h 0d8000h 0e0000h 0e8000h 0f0000h 0f8000h 108000h 100000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1a0000h 1a8000h 1b0000h 1b8000h 1c0000h 1c8000h 1d0000h 1d8000h 1e0000h 1e8000h 1f0000h 1f8000h 1fffffh 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2a0000h 2a8000h 2b0000h 2b8000h 2c0000h 2c8000h 2d0000h 2d8000h 2e0000h 2e8000h 2f0000h 2f8000h 308000h 300000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3a0000h 3a8000h 3b0000h 3b8000h 3c0000h 3c8000h 3d0000h 3d8000h 3e0000h 3e8000h 3f0000h 3f8000h 400000h 408000h 410000h 418000h 420000h 428000h 430000h 438000h 440000h 448000h 450000h 458000h 460000h 468000h 470000h 478000h 480000h 488000h 490000h 498000h 4a0000h 4a8000h 4b0000h 4b8000h 4c0000h 4c8000h 4d0000h 4d8000h 4e0000h 4e8000h 4f0000h 4f8000h 508000h 500000h 510000h 518000h 520000h 528000h 530000h 538000h 540000h 548000h 550000h 558000h 560000h 568000h 570000h 578000h 580000h 588000h 590000h 598000h 5a0000h 5a8000h 5b0000h 5b8000h 5c0000h 5c8000h 5d0000h 5d8000h 5e0000h 5e8000h 5f0000h 5f8000h 5fffffh 600000h 608000h 610000h 618000h 620000h 628000h 630000h 638000h 640000h 648000h 650000h 658000h 660000h 668000h 670000h 678000h 680000h 688000h 690000h 698000h 6a0000h 6a8000h 6b0000h 6b8000h 6c0000h 6c8000h 6d0000h 6d8000h 6e0000h 6e8000h 6f0000h 6f8000h 708000h 700000h 710000h 718000h 720000h 728000h 730000h 738000h 740000h 748000h 750000h 758000h 760000h 768000h 770000h 778000h 780000h 788000h 790000h 798000h 7a0000h 7a8000h 7b0000h 7b8000h 7c0000h 7c8000h 7d0000h 7d8000h 7e0000h 7e8000h 7f0000h 7f8000h 7f9000h 7fa000h 7fb000h 7fc000h 7fd000h 7fe000h 7ff000h 7fffffh 3fffffh bank a bank d bank b bank c bank b bank c
mb84sf6h6h6l2 -70 16 ? flexbank tm architecture ? simultaneous operation note : bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bankc and bank d. bank address (ba) meant to specify each of the banks. bank splits bank 1 bank 2 volume combination volume combination 1 16 mbit bank a 112mbit remember (bank b, c, d) 2 48 mbit bank b 96 mbit remember (bank a, c, d) 3 48 mbit bank c 96 mbit remember (bank a, b, d) 4 16 mbit bank d 112mbit remember (bank a, b, c) case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode 5 autoselect mode read mode 6 program mode read mode 7 erase mode read mode
mb84sf6h6h6l2 -70 17 ? sector address tables (bank a) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0 0 0 0 0 0 0 0 0 0 0 4 000000h to 000fffh sa1 0 0 0 0 0 0 0 0 0 0 1 4 001000h to 001fffh sa2 0 0 0 0 0 0 0 0 0 1 0 4 002000h to 002fffh sa3 0 0 0 0 0 0 0 0 0 1 1 4 003000h to 003fffh sa4 0 0 0 0 0 0 0 0 1 0 0 4 004000h to 004fffh sa5 0 0 0 0 0 0 0 0 1 0 1 4 005000h to 005fffh sa6 0 0 0 0 0 0 0 0 1 1 0 4 006000h to 006fffh sa7 0 0 0 0 0 0 0 0 1 1 1 4 007000h to 007fffh sa8 0 0 0 0 0 0 0 1 x x x 32 008000h to 00ffffh sa9 0 0 0 0 0 0 1 0 x x x 32 010000h to 017fffh sa10 0 0 0 0 0 0 1 1 x x x 32 018000h to 01ffffh sa11 0 0 0 0 0 1 0 0 x x x 32 020000h to 027fffh sa12 0 0 0 0 0 1 0 1 x x x 32 028000h to 02ffffh sa13 0 0 0 0 0 1 1 0 x x x 32 030000h to 037fffh sa14 0 0 0 0 0 1 1 1 x x x 32 038000h to 03ffffh sa15 0 0 0 0 1 0 0 0 x x x 32 040000h to 047fffh sa16 0 0 0 0 1 0 0 1 x x x 32 048000h to 04ffffh sa17 0 0 0 0 1 0 1 0 x x x 32 050000h to 057fffh sa18 0 0 0 0 1 0 1 1 x x x 32 058000h to 05ffffh sa19 0 0 0 0 1 1 0 0 x x x 32 060000h to 06ffffh sa20 0 0 0 0 1 1 0 1 x x x 32 068000h to 06ffffh sa21 0 0 0 0 1 1 1 0 x x x 32 070000h to 077fffh sa22 0 0 0 0 1 1 1 1 x x x 32 078000h to 07ffffh sa23 0 0 0 1 0 0 0 0 x x x 32 080000h to 087fffh sa24 0 0 0 1 0 0 0 1 x x x 32 088000h to 08ffffh sa25 0 0 0 1 0 0 1 0 x x x 32 090000h to 097fffh sa26 0 0 0 1 0 0 1 1 x x x 32 098000h to 09ffffh sa27 0 0 0 1 0 1 0 0 x x x 32 0a0000h to 0a7fffh sa28 0 0 0 1 0 1 0 1 x x x 32 0a8000h to 0affffh sa29 0 0 0 1 0 1 1 0 x x x 32 0b0000h to 0b7fffh sa30 0 0 0 1 0 1 1 1 x x x 32 0b8000h to 0bffffh sa31 0 0 0 1 1 0 0 0 x x x 32 0c0000h to 0c7fffh sa32 0 0 0 1 1 0 0 1 x x x 32 0c8000h to 0cffffh sa33 0 0 0 1 1 0 1 0 x x x 32 0d0000h to 0d7fffh sa34 0 0 0 1 1 0 1 1 x x x 32 0d8000h to 0dffffh sa35 0 0 0 1 1 1 0 0 x x x 32 0e0000h to 0e7fffh sa36 0 0 0 1 1 1 0 1 x x x 32 0e8000h to 0effffh sa37 0 0 0 1 1 1 1 0 x x x 32 0f0000h to 0f7fffh sa38 0 0 0 1 1 1 1 1 x x x 32 0f8000h to 0fffffh
mb84sf6h6h6l2 -70 18 ? sector address tables (bank b) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa39 0 0 1 0 0 0 0 0 x x x 32 100000h to 107fffh sa40 0 0 1 0 0 0 0 1 x x x 32 108000h to 10ffffh sa41 0 0 1 0 0 0 1 0 x x x 32 110000h to 117fffh sa42 0 0 1 0 0 0 1 1 x x x 32 118000h to 11ffffh sa43 0 0 1 0 0 1 0 0 x x x 32 120000h to 127fffh sa44 0 0 1 0 0 1 0 1 x x x 32 128000h to 12ffffh sa45 0 0 1 0 0 1 1 0 x x x 32 130000h to 137fffh sa46 0 0 1 0 0 1 1 1 x x x 32 138000h to 13ffffh sa47 0 0 1 0 1 0 0 0 x x x 32 140000h to 147fffh sa48 0 0 1 0 1 0 0 1 x x x 32 148000h to 14ffffh sa49 0 0 1 0 1 0 1 0 x x x 32 150000h to 157fffh sa50 0 0 1 0 1 0 1 1 x x x 32 158000h to 15ffffh sa51 0 0 1 0 1 1 0 0 x x x 32 160000h to 167fffh sa52 0 0 1 0 1 1 0 1 x x x 32 168000h to 16ffffh sa53 0 0 1 0 1 1 1 0 x x x 32 170000h to 177fffh sa54 0 0 1 0 1 1 1 1 x x x 32 178000h to 17ffffh sa55 0 0 1 1 0 0 0 0 x x x 32 180000h to 187fffh sa56 0 0 1 1 0 0 0 1 x x x 32 188000h to 18ffffh sa57 0 0 1 1 0 0 1 0 x x x 32 190000h to 197fffh sa58 0 0 1 1 0 0 1 1 x x x 32 198000h to 19ffffh sa59 0 0 1 1 0 1 0 0 x x x 32 1a0000h to 1a7fffh sa60 0 0 1 1 0 1 0 1 x x x 32 1a8000h to 1affffh sa61 0 0 1 1 0 1 1 0 x x x 32 1b0000h to 1b7fffh sa62 0 0 1 1 0 1 1 1 x x x 32 1b8000h to 1bffffh sa63 0 0 1 1 1 0 0 0 x x x 32 1c0000h to 1c7fffh sa64 0 0 1 1 1 0 0 1 x x x 32 1c8000h to 1cffffh sa65 0 0 1 1 1 0 1 0 x x x 32 1d0000h to 1d7fffh sa66 0 0 1 1 1 0 1 1 x x x 32 1d8000h to 1dffffh sa67 0 0 1 1 1 1 0 0 x x x 32 1e0000h to 1e7fffh sa68 0 0 1 1 1 1 0 1 x x x 32 1e8000h to 1effffh sa69 0 0 1 1 1 1 1 0 x x x 32 1f0000h to 1f7fffh sa70 0 0 1 1 1 1 1 1 x x x 32 1f8000h to 1fffffh sa71 0 1 0 0 0 0 0 0 x x x 32 200000h to 207fffh sa72 0 1 0 0 0 0 0 1 x x x 32 208000h to 20ffffh sa73 0 1 0 0 0 0 1 0 x x x 32 210000h to 217fffh sa74 0 1 0 0 0 0 1 1 x x x 32 218000h to 21ffffh sa75 0 1 0 0 0 1 0 0 x x x 32 220000h to 227fffh sa76 0 1 0 0 0 1 0 1 x x x 32 228000h to 22ffffh sa77 0 1 0 0 0 1 1 0 x x x 32 230000h to 237fffh
mb84sf6h6h6l2 -70 19 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa78 0 1 0 0 0 1 1 1 x x x 32 238000h to 23ffffh sa79 0 1 0 0 1 0 0 0 x x x 32 240000h to 247fffh sa80 0 1 0 0 1 0 0 1 x x x 32 248000h to 24ffffh sa81 0 1 0 0 1 0 1 0 x x x 32 250000h to 257fffh sa82 0 1 0 0 1 0 1 1 x x x 32 258000h to 25ffffh sa83 0 1 0 0 1 1 0 0 x x x 32 260000h to 267fffh sa84 0 1 0 0 1 1 0 1 x x x 32 268000h to 26ffffh sa85 0 1 0 0 1 1 1 0 x x x 32 270000h to 277fffh sa86 0 1 0 0 1 1 1 1 x x x 32 278000h to 27ffffh sa87 0 1 0 1 0 0 0 0 x x x 32 280000h to 287fffh sa88 0 1 0 1 0 0 0 1 x x x 32 288000h to 28ffffh sa89 0 1 0 1 0 0 1 0 x x x 32 290000h to 297fffh sa90 0 1 0 1 0 0 1 1 x x x 32 298000h to 29ffffh sa91 0 1 0 1 0 1 0 0 x x x 32 2a0000h to 2a7fffh sa92 0 1 0 1 0 1 0 1 x x x 32 2a8000h to 2affffh sa93 0 1 0 1 0 1 1 0 x x x 32 2b0000h to 2b7fffh sa94 0 1 0 1 0 1 1 1 x x x 32 2b8000h to 2bffffh sa95 0 1 0 1 1 0 0 0 x x x 32 2c0000h to 2c7fffh sa96 0 1 0 1 1 0 0 1 x x x 32 2c8000h to 2cffffh sa97 0 1 0 1 1 0 1 0 x x x 32 2d0000h to 2d7fffh sa98 0 1 0 1 1 0 1 1 x x x 32 2d8000h to 2dffffh sa99 0 1 0 1 1 1 0 0 x x x 32 2e0000h to 2e7fffh sa100 0 1 0 1 1 1 0 1 x x x 32 2e8000h to 2effffh sa101 0 1 0 1 1 1 1 0 x x x 32 2f0000h to 2f7fffh sa102 0 1 0 1 1 1 1 1 x x x 32 2f8000h to 2fffffh sa103 0 1 1 0 0 0 0 0 x x x 32 300000h to 307fffh sa104 0 1 1 0 0 0 0 1 x x x 32 308000h to 30ffffh sa105 0 1 1 0 0 0 1 0 x x x 32 310000h to 317fffh sa106 0 1 1 0 0 0 1 1 x x x 32 318000h to 31ffffh sa107 0 1 1 0 0 1 0 0 x x x 32 320000h to 327fffh sa108 0 1 1 0 0 1 0 1 x x x 32 328000h to 32ffffh sa109 0 1 1 0 0 1 1 0 x x x 32 330000h to 337fffh sa110 0 1 1 0 0 1 1 1 x x x 32 338000h to 33ffffh sa111 0 1 1 0 1 0 0 0 x x x 32 340000h to 347fffh sa112 0 1 1 0 1 0 0 1 x x x 32 348000h to 34ffffh sa113 0 1 1 0 1 0 1 0 x x x 32 350000h to 357fffh sa114 0 1 1 0 1 0 1 1 x x x 32 358000h to 35ffffh sa115 0 1 1 0 1 1 0 0 x x x 32 360000h to 367fffh sa116 0 1 1 0 1 1 0 1 x x x 32 368000h to 36ffffh
mb84sf6h6h6l2 -70 20 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa117 0 1 1 0 1 1 1 0 x x x 32 370000h to 377fffh sa118 0 1 1 0 1 1 1 1 x x x 32 378000h to 37ffffh sa119 0 1 1 1 0 0 0 0 x x x 32 380000h to 387fffh sa120 0 1 1 1 0 0 0 1 x x x 32 388000h to 38ffffh sa121 0 1 1 1 0 0 1 0 x x x 32 390000h to 397fffh sa122 0 1 1 1 0 0 1 1 x x x 32 398000h to 39ffffh sa123 0 1 1 1 0 1 0 0 x x x 32 3a0000h to 3a7fffh sa124 0 1 1 1 0 1 0 1 x x x 32 3a8000h to 3affffh sa125 0 1 1 1 0 1 1 0 x x x 32 3b0000h to 3b7fffh sa126 0 1 1 1 0 1 1 1 x x x 32 3b8000h to 3bffffh sa127 0 1 1 1 1 0 0 0 x x x 32 3c0000h to 3c7fffh sa128 0 1 1 1 1 0 0 1 x x x 32 3c8000h to 3cffffh sa129 0 1 1 1 1 0 1 0 x x x 32 3d0000h to 3d7fffh sa130 0 1 1 1 1 0 1 1 x x x 32 3d8000h to 3dffffh sa131 0 1 1 1 1 1 0 0 x x x 32 3e0000h to 3e7fffh sa132 0 1 1 1 1 1 0 1 x x x 32 3e8000h to 3effffh sa133 0 1 1 1 1 1 1 0 x x x 32 3f0000h to 3f7fffh sa134 0 1 1 1 1 1 1 1 x x x 32 3f8000h to 3fffffh
mb84sf6h6h6l2 -70 21 ? sector address tables (bank c) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa135 1 0 0 00000xxx 32 4 00000h to 407fffh sa136 1 0 0 00001xxx 32 40 8000h to 40ffffh sa137 1 0 0 00010xxx 32 4 10000h to 417fffh sa138 1 0 0 00011xxx 32 41 8000h to 41ffffh sa139 1 0 0 00100xxx 32 4 20000h to 427fffh sa140 1 0 0 00101xxx 32 42 8000h to 42ffffh sa141 1 0 0 00110xxx 32 4 30000h to 437fffh sa142 1 0 0 00111xxx 32 43 8000h to 43ffffh sa143 1 0 0 01000xxx 32 4 40000h to 447fffh sa144 1 0 0 01001xxx 32 44 8000h to 44ffffh sa145 1 0 0 01010xxx 32 4 50000h to 457fffh sa146 1 0 0 01011xxx 32 45 8000h to 45ffffh sa147 1 0 0 01100xxx 32 4 60000h to 467fffh sa148 1 0 0 01101xxx 32 46 8000h to 46ffffh sa149 1 0 0 01110xxx 32 4 70000h to 477fffh sa150 1 0 0 01111xxx 32 47 8000h to 47ffffh sa151 1 0 0 10000xxx 32 4 80000h to 487fffh sa152 1 0 0 10001xxx 32 48 8000h to 48ffffh sa153 1 0 0 10010xxx 32 4 90000h to 497fffh sa154 1 0 0 10011xxx 32 49 8000h to 49ffffh sa155 1 0 0 10100xxx 32 4a0000h to 4a7fffh sa156 1 0 0 10101xxx 32 4a 8000h to 4affffh sa157 1 0 0 10110xxx 32 4b0000h to 4b7fffh sa158 1 0 0 10111xxx 32 4b 8000h to 4bffffh sa159 1 0 0 11000xxx 32 4c0000h to 4c7fffh sa160 1 0 0 11001xxx 32 4c 8000h to 4cffffh sa161 1 0 0 11010xxx 32 4d0000h to 4d7fffh sa162 1 0 0 11011xxx 32 4d 8000h to 4dffffh sa163 1 0 0 11100xxx 32 4e0000h to 4e7fffh sa164 1 0 0 11101xxx 32 4e 8000h to 4effffh sa165 1 0 0 11110xxx 32 4f0000h to 4f7fffh sa166 1 0 0 11111xxx 32 4f 8000h to 4fffffh sa167 1 0 1 00000xxx 32 5 00000h to 507fffh sa168 1 0 1 00001xxx 32 50 8000h to 50ffffh sa169 1 0 1 00010xxx 32 5 10000h to 517fffh sa170 1 0 1 00011xxx 32 51 8000h to 51ffffh sa171 1 0 1 00100xxx 32 5 20000h to 527fffh sa172 1 0 1 00101xxx 32 52 8000h to 52ffffh sa173 1 0 1 00110xxx 32 5 30000h to 537fffh
mb84sf6h6h6l2 -70 22 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa174 1 0 1 0 0 1 1 1 x x x 32 538000h to 53ffffh sa175 1 0 1 0 1 0 0 0 x x x 32 540000h to 547fffh sa176 1 0 1 0 1 0 0 1 x x x 32 548000h to 54ffffh sa177 1 0 1 0 1 0 1 0 x x x 32 550000h to 557fffh sa178 1 0 1 0 1 0 1 1 x x x 32 558000h to 55ffffh sa179 1 0 1 0 1 1 0 0 x x x 32 560000h to 567fffh sa180 1 0 1 0 1 1 0 1 x x x 32 568000h to 56ffffh sa181 1 0 1 0 1 1 1 0 x x x 32 570000h to 577fffh sa182 1 0 1 0 1 1 1 1 x x x 32 578000h to 57ffffh sa183 1 0 1 1 0 0 0 0 x x x 32 580000h to 587fffh sa184 1 0 1 1 0 0 0 1 x x x 32 588000h to 58ffffh sa185 1 0 1 1 0 0 1 0 x x x 32 590000h to 597fffh sa186 1 0 1 1 0 0 1 1 x x x 32 598000h to 59ffffh sa187 1 0 1 1 0 1 0 0 x x x 32 5a0000h to 5a7fffh sa188 1 0 1 1 0 1 0 1 x x x 32 5a8000h to 5affffh sa189 1 0 1 1 0 1 1 0 x x x 32 5b0000h to 5b7fffh sa190 1 0 1 1 0 1 1 1 x x x 32 5b8000h to 5bffffh sa191 1 0 1 1 1 0 0 0 x x x 32 5c0000h to 5c7fffh sa192 1 0 1 1 1 0 0 1 x x x 32 5c8000h to 5cffffh sa193 1 0 1 1 1 0 1 0 x x x 32 6d0000h to 5d7fffh sa194 1 0 1 1 1 0 1 1 x x x 32 6d8000h to 5dffffh sa195 1 0 1 1 1 1 0 0 x x x 32 5e0000h to 5e7fffh sa196 1 0 1 1 1 1 0 1 x x x 32 5e8000h to 5effffh sa197 1 0 1 1 1 1 1 0 x x x 32 5f0000h to 5f7fffh sa198 1 0 1 1 1 1 1 1 x x x 32 5f8000h to 5fffffh sa199 1 1 0 0 0 0 0 0 x x x 32 600000h to 607fffh sa200 1 1 0 0 0 0 0 1 x x x 32 608000h to 60ffffh sa201 1 1 0 0 0 0 1 0 x x x 32 610000h to 617fffh sa202 1 1 0 0 0 0 1 1 x x x 32 618000h to 61ffffh sa203 1 1 0 0 0 1 0 0 x x x 32 620000h to 627fffh sa204 1 1 0 0 0 1 0 1 x x x 32 628000h to 62ffffh sa205 1 1 0 0 0 1 1 0 x x x 32 630000h to 637fffh sa206 1 1 0 0 0 1 1 1 x x x 32 638000h to 63ffffh sa207 1 1 0 0 1 0 0 0 x x x 32 640000h to 647fffh sa208 1 1 0 0 1 0 0 1 x x x 32 648000h to 64ffffh sa209 1 1 0 0 1 0 1 0 x x x 32 650000h to 657fffh sa210 1 1 0 0 1 0 1 1 x x x 32 658000h to 65ffffh sa211 1 1 0 0 1 1 0 0 x x x 32 660000h to 667fffh sa212 1 1 0 0 1 1 0 1 x x x 32 668000h to 66ffffh
mb84sf6h6h6l2 -70 23 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa213 1 1 0 01110xxx 32 6 70000h to 677fffh sa214 1 1 0 01111xxx 32 6 78000h to 67ffffh sa215 1 1 0 10000xxx 32 6 80000h to 687fffh sa216 1 1 0 10001xxx 32 6 88000h to 68ffffh sa217 1 1 0 10010xxx 32 6 90000h to 697fffh sa218 1 1 0 10011xxx 32 6 98000h to 69ffffh sa219 1 1 0 10100xxx 32 6a0000h to 6a7fffh sa220 1 1 0 10101xxx 32 6a 8000h to 6affffh sa221 1 1 0 10110xxx 32 6b0000h to 6b7fffh sa222 1 1 0 10111xxx 32 8b 8000h to 6bffffh sa223 1 1 0 11000xxx 32 6c0000h to 6c7fffh sa224 1 1 0 11001xxx 32 6c 8000h to 6cffffh sa225 1 1 0 11010xxx 32 6d0000h to 6d7fffh sa226 1 1 0 11011xxx 32 6d 8000h to 6dffffh sa227 1 1 0 11100xxx 32 6e0000h to 6e7fffh sa228 1 1 0 11101xxx 32 6e 8000h to 6effffh sa229 1 1 0 11110xxx 32 6f0000h to 6f7fffh sa230 1 1 0 11111xxx 32 6f 8000h to 6fffffh
mb84sf6h6h6l2 -70 24 ? sector address tables (bank d) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa231 1 1 1 0 0 0 0 0 x x x 32 700000h to 707fffh sa232 1 1 1 0 0 0 0 1 x x x 32 708000h to 70ffffh sa233 1 1 1 0 0 0 1 0 x x x 32 710000h to 717fffh sa234 1 1 1 0 0 0 1 1 x x x 32 718000h to 71ffffh sa235 1 1 1 0 0 1 0 0 x x x 32 720000h to 727fffh sa236 1 1 1 0 0 1 0 1 x x x 32 728000h to 72ffffh sa237 1 1 1 0 0 1 1 0 x x x 32 730000h to 737fffh sa238 1 1 1 0 0 1 1 1 x x x 32 738000h to 73ffffh sa239 1 1 1 0 1 0 0 0 x x x 32 740000h to 747fffh sa240 1 1 1 0 1 0 0 1 x x x 32 748000h to 74ffffh sa241 1 1 1 0 1 0 1 0 x x x 32 750000h to 757fffh sa242 1 1 1 0 1 0 1 1 x x x 32 758000h to 75ffffh sa243 1 1 1 0 1 1 0 0 x x x 32 760000h to 767fffh sa244 1 1 1 0 1 1 0 1 x x x 32 768000h to 76ffffh sa245 1 1 1 0 1 1 1 0 x x x 32 770000h to 777fffh sa246 1 1 1 0 1 1 1 1 x x x 32 778000h to 77ffffh sa247 1 1 1 1 0 0 0 0 x x x 32 780000h to 787fffh sa248 1 1 1 1 0 0 0 1 x x x 32 788000h to 78ffffh sa249 1 1 1 1 0 0 1 0 x x x 32 790000h to 797fffh sa250 1 1 1 1 0 0 1 1 x x x 32 798000h to 79ffffh sa251 1 1 1 1 0 1 0 0 x x x 32 7a0000h to 7a7fffh sa252 1 1 1 1 0 1 0 1 x x x 32 7a8000h to 7affffh sa253 1 1 1 1 0 1 1 0 x x x 32 7b0000h to 7b7fffh sa254 1 1 1 1 0 1 1 1 x x x 32 7b8000h to 7bffffh sa255 1 1 1 1 1 0 0 0 x x x 32 7c0000h to 7c7fffh sa256 1 1 1 1 1 0 0 1 x x x 32 7c8000h to 7cffffh sa257 1 1 1 1 1 0 1 0 x x x 32 7d0000h to 7d7fffh sa258 1 1 1 1 1 0 1 1 x x x 32 7d8000h to 7dffffh sa259 1 1 1 1 1 1 0 0 x x x 32 7e0000h to 7e7fffh sa260 1 1 1 1 1 1 0 1 x x x 32 7e8000h to 7effffh sa261 1 1 1 1 1 1 1 0 x x x 32 7f0000h to 7f7fffh sa262 1 1 1 1 1 1 1 1 0 0 0 4 7f8000h to 7f8fffh sa263 1 1 1 1 1 1 1 1 0 0 1 4 7f9000h to 7f9fffh sa264 1 1 1 1 1 1 1 1 0 1 0 4 7fa000h to 7fafffh sa265 1 1 1 1 1 1 1 1 0 1 1 4 7fb000h to 7fbfffh sa266 1 1 1 1 1 1 1 1 1 0 0 4 7fc000h to 7fcfffh sa267 1 1 1 1 1 1 1 1 1 0 1 4 7fd000h to 7fdfffh sa268 1 1 1 1 1 1 1 1 1 1 0 4 7fe000h to 7fefffh sa269 1 1 1 1 1 1 1 1 1 1 1 4 7ff000h to 7fffffh
mb84sf6h6h6l2 -70 25 ? sector group address table (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000000 sa0 sga1 00000000001 sa1 sga2 00000000010 sa2 sga3 00000000011 sa3 sga4 00000000100 sa4 sga5 00000000101 sa5 sga6 00000000110 sa6 sga7 00000000111 sa7 sga8 00000001xxx sa8 sga9 00000010xxx sa9 sga10 00000011xxx sa10 sga11 0 0 0 0 0 1 x x x x x sa11 to sa14 sga12 0 0 0 0 1 0 x x x x x sa15 to sa18 sga13 0 0 0 0 1 1 x x x x x sa19 to sa22 sga14 0 0 0 1 0 0 x x x x x sa23 to sa26 sga15 0 0 0 1 0 1 x x x x x sa27 to sa30 sga16 0 0 0 1 1 0 x x x x x sa31 to sa34 sga17 0 0 0 1 1 1 x x x x x sa35 to sa38 sga18 0 0 1 0 0 0 x x x x x sa39 to sa42 sga19 0 0 1 0 0 1 x x x x x sa43 to sa46 sga20 0 0 1 0 1 0 x x x x x sa47 to sa50 sga21 0 0 1 0 1 1 x x x x x sa51 to sa54 sga22 0 0 1 1 0 0 x x x x x sa55 to sa58 sga23 0 0 1 1 0 1 x x x x x sa59 to sa62 sga24 0 0 1 1 1 0 x x x x x sa63 to sa66 sga25 0 0 1 1 1 1 x x x x x sa67 to sa70 sga26 0 1 0 0 0 0 x x x x x sa71 to sa74 sga27 0 1 0 0 0 1 x x x x x sa75 to sa78
mb84sf6h6h6l2 -70 26 (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga28 0 1 0 0 1 0 x x x x x sa79 to sa82 sga29 0 1 0 0 1 1 x x x x x sa83 to sa86 sga30 0 1 0 1 0 0 x x x x x sa87 to sa90 sga31 0 1 0 1 0 1 x x x x x sa91 to sa94 sga32 0 1 0 1 1 0 x x x x x sa95 to sa98 sga33 0 1 0 1 1 1 x x x x x sa99 to sa102 sga34 0 1 1 0 0 0 x x x x x sa103 to sa106 sga35 0 1 1 0 0 1 x x x x x sa107 to sa110 sga36 0 1 1 0 1 0 x x x x x sa111 to sa114 sga37 0 1 1 0 1 1 x x x x x sa115 to sa118 sga38 0 1 1 1 0 0 x x x x x sa119 to sa122 sga39 0 1 1 1 0 1 x x x x x sa123 to sa126 sga40 0 1 1 1 1 0 x x x x x sa127 to sa130 sga41 0 1 1 1 1 1 x x x x x sa131 to sa134 sga42 1 0 0 0 0 0 x x x x x sa135 to sa138 sga43 1 0 0 0 0 1 x x x x x sa139 to sa142 sga44 1 0 0 0 1 0 x x x x x sa143 to sa146 sga45 1 0 0 0 1 1 x x x x x sa147 to sa150 sga46 1 0 0 1 0 0 x x x x x sa151 to sa154 sga47 1 0 0 1 0 1 x x x x x sa155 to sa158 sga48 1 0 0 1 1 0 x x x x x sa159 to sa162 sga49 1 0 0 1 1 1 x x x x x sa163 to sa166 sga50 1 0 1 0 0 0 x x x x x sa167 to sa170 sga51 1 0 1 0 0 1 x x x x x sa171 to sa174
mb84sf6h6h6l2 -70 27 (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga52 1 0 1 0 1 0 x x x x x sa175 to sa178 sga53 1 0 1 0 1 1 x x x x x sa179 to sa182 sga54 1 0 1 1 0 0 x x x x x sa183 to sa186 sga55 1 0 1 1 0 1 x x x x x sa187 to sa190 sga56 1 0 1 1 1 0 x x x x x sa191 to sa194 sga57 1 0 1 1 1 1 x x x x x sa195 to sa198 sga58 1 1 0 0 0 0 x x x x x sa199 to sa202 sga59 1 1 0 0 0 1 x x x x x sa203 to sa206 sga60 1 1 0 0 1 0 x x x x x sa207 to sa210 sga61 1 1 0 0 1 1 x x x x x sa211 to sa214 sga62 1 1 0 1 0 0 x x x x x sa215 to sa218 sga63 1 1 0 1 0 1 x x x x x sa219 to sa222 sga64 1 1 0 1 1 0 x x x x x sa223 to sa226 sga65 1 1 0 1 1 1 x x x x x sa227 to sa230 sga66 1 1 1 0 0 0 x x x x x sa231 to sa234 sga67 1 1 1 0 0 1 x x x x x sa235 to sa238 sga68 1 1 1 0 1 0 x x x x x sa239 to sa242 sga69 1 1 1 0 1 1 x x x x x sa243 to sa246 sga70 1 1 1 1 0 0 x x x x x sa247 to sa250 sga71 1 1 1 1 0 1 x x x x x sa251 to sa254 sga72 1 1 1 1 1 0 x x x x x sa255 to sa258 sga73 1 1 1 1 1 1 0 0 x x x sa259 sga74 1 1 1 1 1 1 0 1 x x x sa260 sga75 1 1 1 1 1 1 1 0 x x x sa261 sga76 11111111000 sa262 sga77 11111111001 sa263 sga78 11111111010 sa264 sga79 11111111011 sa265 sga80 11111111100 sa266 sga81 11111111101 sa267 sga82 11111111110 sa268 sga83 11111111111 sa269
mb84sf6h6h6l2 -70 28 ? sector protection verify autoselect codes table legend : l = v il , h = v ih . see dc characteristics for voltage levels. *1 : outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : a read cycle at address (ba) 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. type a 22 to a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 code (hex) manufactures code ba llllllll 04h device code ba lllllllh 227eh extended device code * 2 ba l l l l h h h l 2218h ba l l l l h h h h 2200h sector group protection sector group addresses llllllhl 01h* 1 indicator bits ba llllllhh dq 7 - factory lock bit 1 = locked, 0 = not locked dq 6 - customer lock bit 1 = locked, 0 = not locked
mb84sf6h6h6l2 -70 29 ? flash memory command definitions legend : ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses latch on the rising edge of the adv pulse or active edge of clk while adv = v il whichever comes first or falling edge of wirte pulse while adv = v il. sa = address of the sector to be erased. the combination of a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address. address setted by a 22 , a 21 , a 20 will select bank a, bank b, bank c and bank d. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data latches on the rising edge of write pulse. sga = sector group address to be protected. hra = address of the hiddenrom area 000000h to 00007fh hrba = bank address of the hiddenrom area (a 22 = a 21 = a 20 = a 19 = a 18 = v il ) (continued) command sequence bus write cy- cles reqd first bus write cycle second write cycle third write cycle fourthwrite cycle fifth write cycle sixth write cycle seventh write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data read / reset 1xxxhf0hrard read / reset 3 555h aah 2aah 55h 555h f0h ra rd autoselect 3 555h aah 2aah 55h (ba) 555h 90h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h erase suspend 1 ba b0h erase resume 1 ba30h set to fast mode 3 555h aah 2aah 55h 555h 20h fast program 2 xxxh a0 pa pd reset from fast mode * 1 2 ba 90h xxxh f0h* 2 set burst mode configuration register 3 555h aah 2aah 55h (cr) 555h c0h query 1 (ba) 55h 98h hiddenrom entry 3 555h aah 2aah 55h 555h 88h hiddenrom program* 3 4 555h aah 2aah 55h 555h a0h (hra) pa pd hiddenrom exit* 3 4 555h aah 2aah 55h 555h 90h xxxh 00h hiddenrom protect* 3 6 555h aah 2aah 55h 555h 60h opbp 68h opbp 48h xxxh rd(0)
mb84sf6h6h6l2 -70 30 (continued) rd (0) = read data bit. if programmed, dq 0 = 1, if erase, dq 0 = 0 opbp = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 1, 1, 0, 1, 0) cr = configuration register address bits a 19 to a 12 . *1: this command is valid during fast mode. *2: this command is valid during hiddenrom mode. *3: the data 00h is also acceptable. notes : address bits a 22 to a 11 = x = h or l for all address commands except for pa, sa, ba, sga, opbp. bus operations are defined in n device bus operations. both read/reset commands are functionally equivalent, resetting the device to the read mode.
mb84sf6h6h6l2 -70 31 2. ac characteristics ? synchronous/burst read *1 : access time is from the last of either stable addresses . *2 : addresses are latched on the active edge of clk. note : test conditions output load : v ccq r =1.65 v to 1.95 v : 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to v cc f timing measurement reference level : input : 0.5 v cc f, output : 0.5 v cc f parameter symbol value unit jedec standard min max latency t iacc 71ns burst access time valid clock to output delay t bacc 11ns address setup time to clk* 1 t acs 4ns address hold time from clk* 2 t ach 6ns data hold time from next clock cycle t bdh 3ns chip enable to ry/by valid t cr 11ns output enable to output valid t oe 11ns chip enable to high-z t cez 8ns output enable to high-z t oez 8ns ce f setup time to clk t ces 4ns ready access time from clk t racc 11ns ce f setup time to adv t cas 0ns adv set up time to clk t avsc 4ns adv hold time to clk t avhc 6ns clk to access resume t cka 11ns clk to high-z t ckz 8ns output enable setup time t oes 4ns read cycle for continuous suspend t rcc 1ms read cycle time t rc 56 ns
mb84sf6h6h6l2 -70 32 ? asynchronous read * : asynchronous access time is from the last of either stable addresses or the falling edge of adv . ? hardware reset (reset ) *1 : access time is from the last of either stable addresses. *2 : addresses are latched on the active edge of clk. note : test conditions : output load : v ccq r =1.65 v to 1.95 v : 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to v cc f timing measurement reference level : input : 0.5 v cc f, output : 0.5 v cc f parameter symbol value unit jedec standard min max read cycle time t rc 56 ns access time from ce f low t ce 56ns asynchronous access time* t acc 56ns output enable to output valid t oe 11ns output enable hold time read t oeh 0ns toggle and data polling 8 ns chip enable to high-z t cez 8ns ce f high during toggle bit polling t ceph 20 ns output enable to high-z t oez 8ns parameter symbol value unit jedec standard min max reset pin low (during embedded algorithms) to read mode * 1 t ready 20s reset pulse width t rp 500 ns reset high time before read * 2 t rh 200 ns power on/off time t ps 0ns
mb84sf6h6h6l2 -70 33 ? write (erase/program) operations *1 : not 100% tested. *2 : see the "erase and programming performance" section in bs12dh datasheet for more information. notes : does not include the preprogramming time. access time is from the last of either stable addresses. addresses are latched on the active edge of clk. parameter symbol value unit jedec standard min typ max write cycle time t avav t wc 56 ns address setup time t avwl t as 0ns address hold time t wlax t ah 20 ns adv low time t avdp 10 ns ce f low to adv high t clah 10 ns data setup time t dvwh t ds 20 ns data hold time t whdx t dh 0ns read recovery time before write t ghwl t ghwl 0ns ce f hold time t wheh t ch 0ns write pulse width t ehwh t wp 20 ns write pulse width high t whwl t wph 20 ns latency between read and write operations t sr/w 0ns programming operation* 1 t whwh1 t whwh1 6 s sector erase operation* 1, * 2 t whwh2 t whwh2 0.5 s v cc f setup time t vcs 50 s ce f setup time to we t elwl t cs 0ns adv set up time to clk t avsc 4ns adv hold time to clk t avhc 6ns adv setup time to we t avsw 4ns adv hold time to we t avhw 6ns address setup time to clk t acs 4ns address hold time to clk t ach 6ns address setup time to adv t aas 4ns address hold time to adv t aah 6ns we low to clk t wlc 0ns adv high to we low t ahwl 5ns clk to we low t cwl 5ns erase time-out time t tow 50 s
mb84sf6h6h6l2 -70 34 ? erase and programming performance notes : typical erase conditions : t a = +25c, v cc f = 1.8 v typical program conditions : t a = +25c, v cc f = 1.8 v, data = checker test conditions : output load : v ccq r =1.65 v to 1.95 v : 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v to v cc f timing measurement reference level : input: 0.5 v cc f, output : 0.5 v cc f parameter value unit remarks min typ max sector erase time 0.5 2 s excludes programming prior to erasure word programming time 6.0 100 s excludes system level overhead chip programming time 50.3 200 s excludes system level overhead erase/program cycle 100,000 cycle
mb84sf6h6h6l2 -70 35 ? synchronous burst mode read (latched by rising active clk) da da + 1 da + n oe dq 15 to dq 0 a 22 to a 0 aa adv ry/by clk cef t ces t acs t avsc t avhc t ach t oes t cr t racc t cez t iacc t acc t bdh 7 cycles for initial access shown. high-z high-z high-z 12 34567 t bacc t cka notes : figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. the device is in synchronous mode.
mb84sf6h6h6l2 -70 36 ? synchronous burst mode read (latched by falling active clk) notes : figure shows total number of wait states set to four cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active falling edge. the device is in synchronous mode. da da + 1 da + n oe dq 15 to dq 0 a 22 to a 0 aa adv ry/by clk cef t ces t acs t avsc t avhc t ach t oes t cr t cez t iacc t acc t bdh 4 cycles for initial access shown. t racc high-z high-z high-z 12345 t bacc t cka
mb84sf6h6h6l2 -70 37 ? 8-word linear burst d0 d1 oe dq 15 to dq 0 a 22 to a 0 aa adv ry/by clk cef t ces t acs t avsc t avhc t ach t oes t cr t iacc t bdh d2 d3 d4 d5 d6 d7 high-z t racc 1 2 34567 t bacc t acc t cez 7 cycles for initial access shown. t cka note : figure assumes 7 wait states for initial access, synchronous read. d 0 to d 7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. see "requirements for synchronous (burst) read operation". the set configuration register command sequence has been written with a 18 = 1; device will output ry/by with valid data.
mb84sf6h6h6l2 -70 38 ? 8-word linear burst with wrap around d6 d7 oe dq 15 to dq 0 a 22 to a 0 aa adv ry/by clk cef t ces t acs t avsc t avhc t ach t oes t cr t iacc t bdh d0 d1 d2 d3 d4 d5 high-z t racc 1 2 34567 t bacc t acc t cez 7 cycles for initial access shown. t cka note : figure assumes 7 wait states for initial access, synchronous read. d 0 to d 7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 7th address in range (a 6 ). see "requirements for synchronous (burst) read operation". the set configuration register command sequence has been written with a 18 = 1; device will output ry/by with valid data.
mb84sf6h6h6l2 -70 39 ? linear burst with ry/by set one cycle before data d1 d0 d2 d3 da + n oe dq 15 to dq 0 a 22 to a 0 aa adv ry/by clk cef t ces t acs t avsc t avhc t ach t oes t cr t racc t cez t iacc t bdh 6 wait cycles for initial access shown. high-z high-z high-z 12 3456 t bacc t acc t cka note : figure assumes 6 wait states for initial access, 66 mhz clock, and synchronous read. the set configuration register command sequence has been written with a 18 = 0; device will output ry/by one cycle before valid data.
mb84sf6h6h6l2 -70 40 ? burst suspend clk suspend resume address oe d20 d20 d21 d22 d23 d24 d25 d26 adv ry/by data t oes t ckz t cka t oes t racc t racc cef v ih v il note : the set configuration register command sequence must be written with a 18 =1; device will output ry/by with valid data. the clock during burst suspend is dont care.
mb84sf6h6h6l2 -70 41 ? burst suspend prior to initial access clk suspend resume address oe 7 6 5 4 3 2 1 d(n) d(n+1) d(n+2) d(n+3) d(n+4) adv ry/by data a(n) t cka t oes cef t racc note : figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence must be written with a 18 =1; device will output ry/by with valid data. the clock during burst suspend is dont care.
mb84sf6h6h6l2 -70 42 ? read cycle for continuous suspend clk suspend resume address oe 7 6 5 4 3 2 1 adv a(n) t cka t oes cef t rcc t rcc d(n) invalid data data ry/by notes : figure assumes 6 wait states for initial access and synchronous read. the set configuration register command sequence must be written with a 18 =1; device will output ry/by with valid data. the clock during burst suspend is dont care. burst plus burst suspend should not last longer than t rcc without relaching an address. after the period of t rcc the device will output invalid data.
mb84sf6h6h6l2 -70 43 ? asynchronous mode read address address stable high-z high-z cef oe we outputs outputs valid t rc t acc t oe t cez t oez t ce t oh t oeh notes : adv is assumed to be v il . configuration register is set to asynchronous mode.
mb84sf6h6h6l2 -70 44 ? reset timings ? power on/off timings (128m burst flash) reset t rp reset timings not during embedded algorithms t ready cef, oe t rh cef, oe reset timings during embedded algorithms reset t rp reset data address valid data out t ps t ps v cc f valid data in 1.65 v t rh t acc 0 v 1.65 v
mb84sf6h6h6l2 -70 45 ? program operation timings at asynchronous mode (we latch) address cef oe we data polling 555h pa pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t oe t cs t ch clk program command sequence (last two cycles) read status data adv data a0h pd dq 7 d out d out t ds t dh t cez t oh v il t avsw t avhw t oez va 3rd bus cycle notes : pa = program address, pd = program data, va = valid address for reading status bits. "in progress" and "complete" refer to status of program operation. a 22 to a 12 are dont care during command sequence unlock cycles. clk is dont care. configuration register is set to asynchronous mode.
mb84sf6h6h6l2 -70 46 ? program operation timings at asynchronous mode (adv latch) oe cef data address adv we clk v cc f 555h pd t aas t aah t wc t wph pa t vcs t wp t ahwl t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp t clah a0h t cs notes : pa = program address, pd = program data, va = valid address for reading status bits. "in progress" and "complete" refer to status of program operation. a 22 to a 12 are dont care during command sequence unlock cycles. clk is dont care. configuration register is set to asynchronous mode. addresses are latched on the rising edge of adv .
mb84sf6h6h6l2 -70 47 ? program operation timings at synchronous mode (we latch) oe cef data address adv we clk v cc f 555h pd t wp t cs t avsw t wc t wph pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avhw a0h t wlc t as t ah notes : pa = program address, pd = program data, va = valid address for reading status bits. in progress and complete refer to status of program operation. a 22 to a 12 are dont care during command sequence unlock cycles. configuration register is set to synchronous mode. addresses are latched on the first of either the falling edge of we or active edge of clk. when "t wlc " is not met then adv /address set up and hold time to clk will be required.
mb84sf6h6h6l2 -70 48 ? program operation timings at synchronous mode (clk latch) oe cef data address adv we clk 555h pd t wp t wc t wph pa t acs t avsc t avhc t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data a0h t cwl t ach t vcs vccf t cas t ds t dh notes : pa = program address, pd = program data, va = valid address for reading status bits. "in progress" and "complete" refer to status of program operation. a 22 to a 12 are dont care during command sequence unlock cycles. configuration register is set to synchronous mode. addresses are latched on the first of either the active edge of clk or the rising edge of adv .
mb84sf6h6h6l2 -70 49 ? chip/sector erase command sequence oe cef data address adv we clk v cc f 2aah 30h t wp t wc t cs t wph sa t vcs t dh t ch in progress t whwh2 va complete va program command sequence (last two cycles) read status data t ds t avsw 55h t wlc t avhw t as t ah 10h for chip erase 555h for chip erase t avhc notes : sa is the sector address for sector erase. address bits a 22 to a 12 are dont cares during unlock cycles in the command sequence. this timing is for synchronous mode.
mb84sf6h6h6l2 -70 50 ?data polling timings/toggle bit timings (during embedded algorithm) we cef oe t oe address adv t oeh t ce t ch t oez t cez status data status data t acc va va notes : status reads in figure are shown as asynchronous mode. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data polling will output true data and the toggle bits will stop toggling.
mb84sf6h6h6l2 -70 51 ? synchronous data polling timings/toggle bit timings cef clk adv address oe data ry/by status data status data va va t iacc t iacc notes : the timings are similar to synchronous read timings. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. ry/by is active with data (a 18 = 0 in the burst mode configuration register). when a 18 = 1 in the burst mode configuration register, ry/by is active one clock cycle before data.
mb84sf6h6h6l2 -70 52 ? example of wait states insertion (non-handshaking device) data adv oe clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following adv falling edge rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 wait state decoding addresses: a 14 , a 13 , a 12 = "101" t 5 programmed, 7 total a 14 , a 13 , a 12 = "100" t 4 programmed, 6 total a 14 , a 13 , a 12 = "011" t 3 programmed, 5 total a 14 , a 13 , a 12 = "010" t 2 programmed, 4 total a 14 , a 13 , a 12 = "001" t 1 programmed, 3 total a 14 , a 13 , a 12 = "000" t 0 programmed, 2 total note : figure assumes address d0 is not at an address boundary, active clock edge is rising, and wait state is set to "101".
mb84sf6h6h6l2 -70 53 ? bank-to-bank read/write cycle timings oe cef we t oeh data address adv pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ceph t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph note : breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. the system should read status twice to ensure valid information.
mb84sf6h6h6l2 -70 54 n n n n 128m fcram characteristics for mcp 1. state diagram note : assuming all the parameters specified in 3. ac characteristics in n 128m fcram characteristics for mcp are satisfied. refer to 2. functial description and 3. ac characteristics for details. asynchronous operation (page mode) synchronous operation (burst mode) common state cr set power down standby standby standby output disable write read power up pause time ce2r = l ce2r = h ce 1r = l ce 1r = h ce2r = ce 1r = h ce 1r = l & oe = l ce 1r = l & we = l ce 1r = h ce 1r = h oe = l we = h oe = h we = l address change or byte control byte control byte control @oe = l standby write read ce2r = ce 1r = h ce 1r = l, adv low pulse, & oe = l ce 1r = h adv low pulse adv low pulse (@bl = 8 or 16, and after burst operationis completed) ce 1r = h read suspend oe = h we = l adv low pulse ? initial/standby state ? asynchronous operation ? synchronous operation power down ce2r = l ce2r = h @m = 0 @m = 1 write suspend we = h oe = l ce 1r = l, adv low pulse, & we = l ce 1r = h ce 1r = h
mb84sf6h6h6l2 -70 55 2. functional description this device supports asynchronous page read & normal write operation and synchronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configuable option. ?power-up it is required to follow the power-up timing to start executing proper device operation. refer to power-up timing. after power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. ? configuration registe r the configuration register (cr) is used to configure the type of device function among optional features. each selection of features is set through cr set sequence after power-up. if cr set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default con- figuration. ? cr set sequence the cr set requires total 6 read/write operation with unique address. between each read/write operation requires that device being in standby mode. following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the cr set is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write to msb. the data of forth and fifth cycle is dont-care. if the forth or fifth cycle is written into different address, the cr set is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. and read data (rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, it should perform the cr set sequence prior to regular read/write operation if necessary to change from default configuration. cycle # operation address data 1st read 7fffffh (msb) read data (rda) 2nd write 7fffffh rda 3rd write 7fffffh rda 4th write 7fffffh x 5th write 7fffffh x 6th read address key read data (rdb)
mb84sf6h6h6l2 -70 56 ? address key the address key has the following format. *1 : a 22 , a 21 , a 8 , and a 6 to a 0 must be all "1" in any cases. *2 : it is prohibited to apply this key. *3 : if m=0, all the registers must be set with appropriate key input at the same time. *4 : if m=1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be "1". *5 : burst read & single write is not supported at we single clock pulse control. address pin register name function key description note a 22 to a 21 1 unused bits must be 1 *1 a 20 to a 19 ps partial size 00 32m partial 01 16m partial 10 reserved for future use *2 11 sleep [default] a 18 to a 16 bl burst length 000 reserved for future use *2 001 reserved for future use *2 010 8 words 011 16 words 100 reserved for future use *2 101 reserved for future use *2 110 reserved for future use *2 111 continuous a 15 mmode 0 synchronous mode (burst read / write) *3 1 asynchronous mode[default] (page read / normal write) *4 a 14 to a 12 rl read latency 000 reserved for future use *2 001 3 clocks 010 4 clocks 011 5 clocks 1xx reserved for future use *2 a 11 bs burst sequence 0 reserved for future use *2 1 sequential a 10 sw single write 0 burst read & burst write 1 burst read & single write *5 a 9 ve valid clock edge 0 falling clock edge 1 rising clock edge a 8 1 unused bits muse be 1 *1 a 7 wc write control 0 we single clock pulse control without write suspend function *5 1 we level control with write suspend function a 6 to a 0 1 unused bits must be 1 *1
mb84sf6h6h6l2 -70 57 ?power down the power down is low power idle state controlled by ce2r. ce2r low drives the device in power down mode and mains low power idle state as long as ce2r is kept low. ce2r high resume the device from power down mode. this device has three power down modes, sleep, 16m partial, and 32m partial. the selection of power down mode is set through cr set sequence. each mode has following data retention features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to perform cr set sequence to set to sleep mode after power-up in case of asynchronous operation. mode data retention size retention address sleep [default] no n/a 16m partial 16m bit 000000h to 0fffffh 32m partial 32m bit 000000h to 1fffffh
mb84sf6h6h6l2 -70 58 ? burst read/write operation synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. configuration register set is required to perform burst read & write operation after power- up. once cr set sequence is performed to select synchronous burst mode, the device is configured to synchro- nous burst read/write operation mode with corresponding rl and bl that is set through cr set sequence together with operation mode. in order to perform synchronous burst read & write operation, it is required to control new signals, clk, adv and wait that low power srams dont have. address adv clk dq valid ce 1r oe wait high-z high-z rl bl we high address adv clk dq ce 1r oe wait high-z high-z rl-1 bl d 1 we high ? burst read operation ? burst write operation valid d 2 d bl q 1 q 2 q bl
mb84sf6h6h6l2 -70 59 ? clk input function the clk is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. the clk input increments device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data out. during synchronous operation mode, clk input must be supplied except for standby state and power down state. clk is dont care during asynchronous operation. ?adv input function the adv is input signal to indicate valid address presence on address inputs. it is applicable to synchronous operation as well as asynchronous operation. adv input is active during ce 1r = l and ce 1r = h disables adv input. all the address are determined on the positive edge of adv . during synchronous burst read/write operation, adv = h disables all address inputs. once adv is brought to high after valid address latch, it is inhibited to bring adv low until the end of burst or until burst operation is terminated. adv low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. during asynchronous operation, adv = h also disables all address inputs. adv can be tied to low during asynchronous operation and it is not necessary to control adv to high. ?wait output function the wait is output signal to indicate data bus status when the device is operating in synchronous burst mode. during burst read operation, wait output is enabled after specified time duration from oe = l. wait output low indicates data out at next clock cycle is invalid, and wait output becomes high one clock cycle prior to valid data out. during oe read suspend, wait output doesnt indicate data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if final read data out is suspended, wait output become high impedance after specified time duration from oe = h. during burst write operation, wait output is enabled to high level after specified time duration from we = l and kept high for entire write cycles including we write suspend. the actual write data latching starts on the appropriate clock edge with respect to valid click edge, read latency and burst length. during we write suspend, wait output doesnt indicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data in is suspended, wait output become high impedance after specified time duration from we = h. this device doesnt incur additional delay against accrossing device-row boundary or internal refresh orepation. therefore, the burst operation is always started after fixed latency with respect to read latency. and there is no wait ting cycle asserted in the middle of burst operation except for burst suspend by oe brought to high or we brought to high. thus, once wait output is enabled and brought to high, wait output keep high level until the end of burst or until the burst operation is terminated. when the device is operating in asynchronous mode, wait output is always in high impedance.
mb84sf6h6h6l2 -70 60 ?latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. it is set through cr set sequence after power-up. once specific rl is set through cr set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to rl-1. the burst operation is always started after fixed latency with respect to read latency set in cr. address adv clk valid 0 12 345 rl = 3 dq [out] dq [in] ce 1r oe or we wait wait 6 rl = 4 dq [out] dq [in] wait wait rl = 5 dq [out] dq [in] wait wait high-z high-z high-z high-z high-z high-z q 4 q 3 q 2 q 1 d 5 d 5 d 4 d 3 d 2 d 1 q 1 q 2 q 3 q 4 d 1 d 2 d 3 d 4 d 5 q 1 q 2 q 3 d 1 d 2 d 3 d 4 q 5
mb84sf6h6h6l2 -70 61 ? address latch by adv the adv indicates valid address presence on address inputs. during synchronous burst read/write operation mode, all the address are determined on the positive edge of adv when ce 1r = l. the specified minimum value of adv = l setup time and hold time against valid edge of clock where rl count begin must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the negative edge of adv or negative edge of ce 1r whichever comes late. and the determined valid address must not be changed during adv = l period. ? burst length burst length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. it can be set on 8, 16 words boundary or continuous for entire address through cr set sequence. the burst type is sequential that is incremental decoding scheme within a boundary address. starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). after completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. when continuous burst length is set, read/write is endless unless it is terminated by the positive edge of ce 1r. ?single write single write is synchronous write operation with burst length =1. the device can be configured either to "burst read & single write" or to "burst read & burst write" through cr set sequence. once the device is configured to "burst read & single write" mode, the burst length for syncronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accordance with bl values set in cr. ?write control the device has two type of we singal control method, "we level control" and "we single clock pulse control", for synchronous write operation. it is configured through cr set sequence. address adv clk valid 0 12 345 ce 1r we 6 rl = 5 dq [in] wait we dq [in] wait high-z t wld high-z t wsck t ckwh t wltv t wltv we level control we single clock pulse control d 4 d 3 d 2 d 1 d 1 d 2 d 3 d 4
mb84sf6h6h6l2 -70 62 ? burst read suspend burst read operation can be suspended by oe high pulse. during burst read operation, oe brought to high suspends burst read operation. once oe is brought to high with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output become high impedance after specified time duration. it is inhibited to suspend the first data out at the beginning of burst read. oe brought to low resumes burst read operation. once oe is brought to low, data output become valid after specified time duration, and internal address counter is reactivated. the last data out being suspended as the result of oe = h and first data out as the result of oe = l are the from the same address. ? burst write suspend burst write operation can be suspended by we high pulse. during burst write operation, we brought to high suspends burst write operation. once we is brought to high with the specified set up time against clock where the data being suspended, device internal counter is suspended, data input is ignored. it is inhibited to suspend the first data input at the beginning of burst write. we brought to low resumes burst write operation. once we is brought to low, data input become valid after specified time duration, and internal address counter is reactivated. the write address of the cycle where data being suspended and the first write address as the result of we = l are the same address. burst write suspend function is available when the device is operating in we level controlled burst write only. dq oe clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait t cktv q 4 q 2 dq we d 1 t dhck t dsck d 2 d 3 t dsck d 4 wait high clk t ckwh t wsck t ckwh t wsck t dsck t dhck t dhck d 2 t dsck
mb84sf6h6h6l2 -70 63 ? burst read termination burst read operation can be terminated by ce 1r brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by ce 1r = h. it is inhibited to terminate burst read before first data out is completed. in order to guarantee last data output, the specified minimum value of ce 1r = l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. ? burst write termination burst write operation can be terminated by ce 1r brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce 1r = h. it is inhibited to terminate burst write before first data in is completed. in order to guarantee last write data being latched, the specified minimum values of ce 1r = l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. address adv dq oe clk valid ce 1r wait q 1 q 2 t ohz t ac t ckqx t ckclh t trb t ckoh t chz high-z address adv dq we clk valid ce 1r wait t ckclh t trb t ckwh t chz high-z d 2 d 1 t dhck t dhck t dsck t dsck
mb84sf6h6h6l2 -70 64 3. ac characteristics (under recommended operating conditions unless otherwise noted) ? asynchronous read operation (page mode) *1 : maximum value is applicable if ce 1r is kept at low without change of address input of a 3 to a 22 . if needed by system operation, please contact local fujitsu representative for the relaxation of 1s limitation. *2 : address should not be changed within minimum t rc . *3 : the output load 50 pf with 50 w termination to v ccq r 0.5 v. *4 : the output load 5pf without any other load. *5 : applicable to a 3 to a 22 when ce 1r is kept at low. *6 : applicable only to a 0 , a 1 and a 2 when ce 1r is kept at low for the page address access. *7 : in case page read cycle is continued with keeping ce 1r stays low, ce 1r must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. *8 : t vpl is specified from the negative edge of either ce 1r or adv whichever comes late. *9 : applicable when at least two of address inputs among applicable are switched from previous state. *10 : t rc (min) and t prc (min) must be satisfied. parameter symbol value unit notes min max read cycle time t rc 70 1000 ns *1, *2 ce 1r access time t ce 70ns *3 oe access time t oe 40ns *3 address access time t aa 70ns*3, *5 adv access time t av 70 ns *3 lb , ub access time t ba 30ns *3 page address access time t paa 20ns*3, *6 page read cycle time t prc 20 1000 ns *1, *6, *7 output data hold time t oh 5ns *3 ce 1r low to output low-z t clz 5ns *4 oe low to output low-z t olz 0ns *4 lb , ub low to output low-z t blz 0ns *4 ce 1r high to output high-z t chz 20ns *3 oe high to output high-z t ohz 20ns *3 lb , ub high to output high-z t bhz 20ns *3 address setup time to ce 1r low t asc C5 ns address setup time to oe low t aso 10 ns adv low pulse width t vpl 10 ns *8 address hold time from adv high t ahv 5ns address invalid time t ax 10ns*5, *9 address hold time from ce 1r high t chah C5 ns *10 address hold time from oe high t ohah C5 ns ce 1r high pulse width t cp 15 ns
mb84sf6h6h6l2 -70 65 ? asynchronous write operation *1 : maximum value is applicable if ce 1r is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujitsu representative for the relaxation of 1s limitation. *2 : minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ). *3 : write pulse is defined from high to low transition of ce 1r, we or lb / ub , whichever occurs last. *4 : t vpl is specified from the negative edge of either ce 1r or adv whichever comes late. *5 : write recovery is defined from low to high transition of ce 1r, we or lb / ub , whichever occurs first. *6 : if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5 ns after ce 1r is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. *7 : if oe is low after new address input, read cycle is initiated. in other word, oe must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol value unit notes min max write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0ns *3 adv low pulse width t vpl 10 ns *4 address hold time from adv high t ahv 5ns ce1 r write pulse width t cw 45 ns *3 we write pulse width t wp 45 ns *3 lb , ub write pulse width t bw 45 ns *3 ce 1r write recovery time t wrc 15 ns *5 we write recovery time t wr 15 1000 ns *5 lb , ub write recovery time t br 15 1000 ns *5 data setup time t ds 15 ns data hold time t dh 0ns oe high to ce 1r low setup time for write t ohcl C5 ns *6 oe high to address setup time for write t oes 0ns *7 lb , ub write pulse overlap t bwo 30 ns ce 1r high pulse width t cp 15 ns
mb84sf6h6h6l2 -70 66 ? synchoronous operation - clock input (burst mode) *1 : clock period is defined between valid clock edge. *2 : clock rise/fall time is defined between v ih min and v il max. ? synchronous operation - address latch (burst mode) *1 : t ascl is applicable if ce 1 brought to low after adv is brought to low under the condition where t vlcl is satisfied. the both of t ascl and t asvl must be satisfied if t vlcl is not satisfied. *2 : t vpl is specified from the negative edge of either ce 1 or adv whichever comes late. *3 : applicable to the 1st valid clock edge. parameter symbol value unit notes min max clock period rl = 5 t ck 13 ns *1 rl = 4 18 ns *1 rl = 3 30 ns *1 clock high time t ckh 4ns clock low time t ckl 4ns clock rise/fall time t ckt 3ns *2 parameter symbol value unit notes min max address setup time to adv low t asvl C5 ns *1 address setup time to ce 1r low t ascl C5 ns *1 address hold time from adv high t ahv 5ns adv low pulse width t vpl 10 ns *2 adv low setup time to clk t vsck 5ns *3 adv low setup time to ce 1r low t vlcl 5ns *1 ce 1 low setup time to clk t clck 5ns *3 adv low hold time from clk t ckvh 1ns *3 burst end adv high hold time from clk t vhvl 13 ns
mb84sf6h6h6l2 -70 67 ? synchronous read operation (burst mode) *1 : the output load 50 pf with 50 w termination to v ccq r 0.5 v. *2 : the output load 5 pf without any other load. *3 : once they are determined, they must not be changed until the end of burst. *4 : defined from the low to high transition of ce 1r to the high to low transition of either adv or ce 1r whichever occurs late. parameter symbol value unit notes min max burst read cycle time t rcb 8000 ns clk access time t ac 11ns*1 output hold time from clk t ckqx 3ns*1 ce 1r low to wait low t cltl 520ns*1 oe low to wait low t oltl 020ns*1 adv low to wait low t vltl 020ns*1 clk to wait valid time t cktv 11ns*1 wait valid hold time from clk t cktx 3ns*1 ce1 r low to output low-z t clz 5ns*2 oe low to output low-z t olz 0ns*2 lb , ub low to output low-z t blz 0ns*2 ce 1r high to output high-z t chz 20ns*1 oe high to output high-z t ohz 20ns*1 lb , ub high to output high-z t bhz 20ns*1 ce 1r high to wait high-z t chtz 20ns*1 oe high to wait high-z t ohtz 20ns*1 oe low setup time to 1st data-out t olq 30 ns ub , lb setup time to 1st data-out t bsq 26 ns *3 oe setup time to clk t osck 5ns oe hold time from clk t ckoh 5ns burst end ce 1r low hold time from clk t ckclh 5ns burst end ub , lb hold time from clk t ckbh 5ns burst terminate recovery time bl = 8,16 t trb 26 ns *4 bl = continuous 70 ns *4
mb84sf6h6h6l2 -70 68 ? synchronous write operation (burst mode) *1 : defined from the valid input edge to the high to low transition of either adv , ce 1r, or we , whichever occurs last. and once they are determined, they must not be changed until the end of burst. *2 : the output load 50 pf with 50 w termination to v ccq r 0.5 v. *3 : the output load 5 pf without any other load. *4 : defined from the valid clock edge where last data-in being latched at the end of burst write to the high to low transition of either adv or ce 1r whichever occurs late for the next access. *5 : defined from the low to high transition of ce 1r to the high to low transition of either adv or ce 1r whichever occurs late for the next access. parameter symbol value unit notes min max burst write cycle time t wcb 8000 ns data setup time to clock t dsck 5ns data hold time from clk t dhck 3ns we low setup time to 1st data in t wld 30 ns ub , lb setup time for write t bs C5 ns *1 we setup time to clk t wsck 5ns we hold time from clk t ckwh 5ns ce 1r low to wait high t clth 520ns*2 we low to wait high t wlth 020ns*2 ce 1r high to wait high-z t chtz 20ns*2 we high to wait high-z t whtz 20ns*2 burst end ce 1r low hold time from clk t ckclh 5ns burst end ce 1r high setup time to next clk t chck 5ns burst end ub , lb hold time from clk t ckbh 5ns burst write recovery time t wrb 26 ns *3 burst terminate recovery time bl = 8,16 t trb 26 ns *4 bl = continuous t trb 70 ns *4
mb84sf6h6h6l2 -70 69 ? power down parameters *1 : applicable also to power-up. *2 : applicable when partial mode is set. ? other timing parameters *1 : some data might be written into any address location if t chwx (min) is not satisfied. *2 : except for clock input transition time. *3 : the input transition time (t t ) at ac testing is shown in below. if actual t t is longer than specified values, it may violate ac specification of some timing parameters. parameter symbol value unit note min max ce2r low setup time for power down entry t csp 20 ns *1 ce2r low hold time after power down entry t c2lp 70 ns *1 ce 1r high hold time following ce2r high after power down exit [sleep mode only] t chh 300 s *1 ce 1r high hold time following ce2r high after power down exit [not in sleep mode] t chhp 1s*2 ce 1r high setup time following ce2r high after power down exit t chs 0ns*1 parameter symbol value unit note min max ce 1r high to oe invalid time for standby entry t chox 10 ns ce 1r high to we invalid time for standby entry t chwx 10 ns *1 ce2r high hold time after power-up t c2hl 50 s ce 1r high hold time following ce2r high after power-up t chh 300 s input transition time (except for clk) t t 125ns*2, *3
mb84sf6h6h6l2 -70 70 ? ac test conditions ? ac measurement output load circuit description symbol test setup value unit note input high level v ih v ccq r 0.8 v input low level v il v ccq r 0.2 v input timing measurement level v ref v ccq r 0.5 v input transition time async. t t between v il and v ih 5ns sync. 3 ns device under test v cc r v cc r 0.5 v v ss out 0.1 f 50 pf 50 w v ccq r v ss 0.1 f
mb84sf6h6h6l2 -70 71 ? asynchronous read timing #1-1 (basic timing) ? asynchronous read timing #1-2 (basic timing) t ce valid data output address ce 1r dq (output) oe t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz adv low note : this timing diagram assumes ce2r = h and we = h. t ce valid data output address ce 1r dq (output) oe t chz t rc t olz t cp t asc t asc t ohz t oh t bhz lb / ub t oe t ba t blz adv address valid t ahv t vpl t av note : this timing diagram assumes ce2r = h and we = h.
mb84sf6h6h6l2 -70 72 ? asynchronous read timing #2 (oe & address access) ? asynchronous read timing #3 (lb / ub byte access) t aa valid data output address ce 1r dq (output) lb / ub t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe t ax low t aa t ohah t aso note : this timing diagram assumes ce2r = h, adv = l and we = h. t aa valid data output address ce 1r, oe dq 7 to dq 0 (output) ub t bhz t ba t rc t blz address valid valid data output t bhz t oh lb t ax low t ba t ax dq 15 to dq 8 (output) t blz t ba t blz t oh t bhz t oh valid data output note : this timing diagram assumes ce2r = h, adv = l and we = h.
mb84sf6h6h6l2 -70 73 ? asynchronous read timing #4 (page address access after ce 1r control access) ? asynchronous read timing #5 (random and page address access) valid data output (normal access) address (a 2 to a 0 ) ce 1r dq (output) oe t chz t ce t rc t clz address valid valid data output (page access) address t prc t oh t oh t chah t paa address (a 22 to a 3 ) address valid lb / ub t paa t oh t prc t paa t prc t oh address address t rc adv t asc note : this timing diagram assumes ce2r = h and we = h. valid data output (normal access) address (a 2 to a 0 ) ce 1r dq (output) oe t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a 22 to a 3 ) address valid lb / ub t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso notes : this timing diagram assumes ce2r = h, adv = l and we = h. either or both lb and ub must be low when both ce 1r and oe are low.
mb84sf6h6h6l2 -70 74 ? asynchronous write timing #1-1 (basic timing) ? asynchronous write timing #1-2 (basic timing) t as valid data input address ce 1r dq (input) we t dh t ds t wc t wrc t wp t cw lb , ub t as t bw address valid t as t as t br oe t ohcl t as t as t wr adv low note : this timing diagram assumes ce2r = h and adv = l. t as valid data input address ce 1r dq (input) we t dh t ds t wc t wrc t wp t cw lb , ub t as t bw address valid t as t as t br oe t ohcl t as t as t wr adv t vp04.3.12l t ahv note : this timing diagram assumes ce2r = h.
mb84sf6h6h6l2 -70 75 ? asynchronous write timing #2 (we control) ? asynchronous write timing #3-1 (we / lb / ub byte write control) t as address we ce 1r t wc t wr t wp lb , ub address valid t as t wr t wp valid data input dq (input) t dh t ds oe t oes t ohz t wc valid data input t dh t ds low address valid t ohah note : this timing diagram assumes ce2r = h and adv = l. t as address we ce 1r t wc t br t wp lb address valid t as t br t wp valid data input dq 0 to dq 7 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 8 to dq 15 (input) note : this timing diagram assumes ce2r = h, adv = l and oe = h.
mb84sf6h6h6l2 -70 76 ? asynchronous write timing #3-2 (we / lb / ub byte write control) ? asynchronous write timing #3-3 (we / lb / ub byte write control) t as address we ce 1r t wc t wr t bw lb address valid t as t wr t bw valid data input dq 0 to dq 7 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 8 to dq 15 (input) note : this timing diagram assumes ce2r = h, adv = l and oe = h. t as address we ce 1r t wc t br t bw lb address valid t as t br t bw valid data input dq 0 to dq 7 (input) t dh t ds ub t wc valid data input t dh t ds low address valid dq 8 to dq 15 (input) note : this timing diagram assumes ce2r = h, adv = l and oe = h.
mb84sf6h6h6l2 -70 77 ? asynchronous write timing #3-4 (we / lb / ub byte write control) ? asynchronous read / write timing #1-1 (ce 1r control) t as address we ce 1r t wc t br t bw lb address valid t as t br t bw dq 0 to dq 7 (input) t dh t ds ub t wc t dh t ds low address valid dq 8 to dq 15 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo note : this timing diagram assumes ce2r = h, adv = l and oe = h. read data output address ce 1r dq we t wc t cw oe t ohcl ub , lb t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh notes : this timing diagram assumes ce2r = h and adv = l. write address is valid from either ce 1r or we of last falling edge.
mb84sf6h6h6l2 -70 78 ? asynchronous read / write timing #1-2 (ce 1r / we / oe control) ? asynchronous read / write timing #2 (oe , we control) read data output address ce 1r dq we t wc t wp oe t ohcl ub , lb t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output notes : this timing diagram assumes ce2r = h and adv = l. oe can be fixed low during write operation if it is ce 1r controlled write at read-write-read sequence. read data output address ce 1r dq we t wc t wp oe ub , lb t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah notes : this timing diagram assumes ce2r = h and adv = l. ce 1r can be tied to low for we and oe controlled operation.
mb84sf6h6h6l2 -70 79 ? asynchronous read / write timing #3 (oe , we , lb , ub control) ? clock input timing read data output address ce 1r dq we t wc t bw oe ub , lb t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes notes : this timing diagram assumes ce2r = h and adv = l. ce 1r can be tied to low for we and oe controlled operation. clk t ck t ckh t ckl t ckt t ckt t ck notes : stable clock input must be required during ce 1r = l. t ck is defined between valid clock edge. t ckt is defined between v ih min and v il max.
mb84sf6h6h6l2 -70 80 ? address latch timing (synchronous mode) clk adv address ce 1r t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh notes : case #1 is the timing when ce 1r is brought to low after adv is brought to low. case #2 is the timing when adv is brought to low after ce 1r is brought to low. t vpl is specified from the negative edge of either ce 1r or adv whichever comes late. at least one valid clock edge must be input during adv = l. t vsck and t clck are applied to the 1st valid clock edge during adv = l.
mb84sf6h6h6l2 -70 81 ? synchronous read timing #1 (oe control) t ahv address adv dq we oe lb , ub clk valid ce 1r t asvl t vpl t clck t ascl wait q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 82 ? synchronous read timing #2 (ce 1r control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 83 ? synchronous read timing #3 (adv control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl wait q 1 t ac t ckqx t ac t cktv rl = 5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 84 ? synchronous write timing #1 (we level control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait high high-z rl = 5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 85 ? synchronous write timing #2 (we single clock pulse control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait high high-z rl = 5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 86 ? synchronous write timing #3 (adv control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl wait high rl = 5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh high t ckvh t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 87 ? synchronous write timing #4 (we level control, single write) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait high high-z rl = 5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh notes : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and single write operation. write data is latched on the valid clock edge. t asvl
mb84sf6h6h6l2 -70 88 ? synchronous read to write timing #1 (ce 1 control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait t vsck t bs t cp rl = 5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 89 ? synchronous read to write timing #2(adv control) address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl wait t bs rl = 5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 90 ? synchronous write to read timing #1 (ce 1r control) d bl address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl t clck t ascl wait t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t chtz high-z t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 91 ? synchronous write to read timing #2 (adv control) d bl address adv dq we oe lb , ub clk valid ce 1r t asvl t ahv t vpl wait low t vsck rl = 5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t whtz high-z t ckvh note : this timing diagram assumes ce2r = h, the valid clock edge on rising edge and bl = 8 or 16.
mb84sf6h6h6l2 -70 92 ? power-up timing #1 ? power-up timing #2 ce 1r v ccq r 0 v ce2r t chh * 3 v cc r 0 v *2 v cc min* 1, * 2 v ccq min* 1 *2 *1 : v ccq r shall be applied and reach the specified minimum level prior to v cc r applied. *2 : the both of ce 1r and ce2r shall be brought to high together with v ccq r prior to v cc r applied. otherwise power-up timing#2 must be applied for proper operation. *3 : the t chh specifies after v cc r reaches specified minimum level and applicable to both ce 1r and ce2r. ce 1r v ccq r v ccq r min* 1 0 v ce2r t chh v cc r 0 v v cc r min* 1 t c2hl * 2 t chs t csp t c2lp t c2hl * 2 *3 *1 : v ccq r shall be applied and reach specified minimum level prior to v cc applied. *2 : the t c2hl specifies from ce2r low to high transition after v cc r reaches specified minimum level. if ce2r became high prior to v cc r reached specified minimum level, t c2hl is defined from v cc r minimum. *3 : ce 1r shall be brought to high prior to or together with ce2r low to high transition.
mb84sf6h6h6l2 -70 93 ? power down entry and exit timing ? standby entry timing after read or write t csp ce 1r power down entry ce2r t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z note : this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. t chox ce 1r oe we active (read) standby active (write) standby t chwx note : both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce 1r low to high transition.
mb84sf6h6h6l2 -70 94 ? configuration register set timing #1 (asynchronous operation) address ce 1r dq* 3 we t rc oe lb , ub rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t wc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc ) *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. *3 : after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode respectively.
mb84sf6h6h6l2 -70 95 ? we configuration register set timing #2 (synchronous operation) address adv dq we oe lb , ub clk ce 1r msb msb msb msb msb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb t trb rl rl-1 rl-1 rl-1 rl-1 rl notes : the all address inputs must be high from cycle #1 to #5. the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. rdb x x rda rda rda cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6
mb84sf6h6h6l2 -70 96 n n n n pin capacitance note: test conditions t a = + 25c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of package create acute angles. n n n n caution the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protect function are used, then the high voltage (v id ) can be applied to reset . without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol condition value unit min typ max input capacitance c in v in = 0 ?? 20.0 pf output capacitance c out v out = 0 ?? 25.0 pf control pin capacitance c in2 v in = 0 ?? 25.0 pf
mb84sf6h6h6l2 -70 97 n n n n ordering information mb84sf6h6h6l 2 -70 pbs device number/descripton 128mega-bit (8m x 16bit) burst flash memory 1.8v-only read, program, and erase 128mega-bit (8m x 16bit) burst flash memory 1.8v-only read, program, and erase 128 mega-bit (8m x 16bit) fcram 1.8v i/o supply voltage 3.0v core supply voltage package type pbs = 115-ball bga speed option device revision
mb84sf6h6h6l2 -70 98 n n n n package dimension 115-ball plastic fbga (bga-115p-m03) dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited b115003s-c-1-1 12.00 0.10(.472 .004) 9.00 0.10 (.354 .004) (.049 .004) 1.25 0.10 (seated height) a b c d e f g h j k l m 1 2 3 4 5 6 7 8 m s ab b ref 0.80(.031) ref 0.40(.016) s s 0.08(.003) 9 10 n p 0.10 0.05 (.004 .002) (stand off) 0.40(.016) ref a 0.80(.031) ref 115- ? 0.40 +.004 C.002 115- ?. 016 ? 0.08(.003) b s 0.20(.008) 0.20(.008) s a s 0.08(.003) index-mark area +.010 C0.05
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